embedded award 2024: Hardware nominees
3/13/2024 Expert knowledge embedded world

embedded award 2024: Hardware nominees

Increasing softwareisation does not change the fact that hardware platforms are the basis for every embedded system. The fact that this category had the most entries for the embedded award this year underlines the importance of embedded hardware products. These three nominees convinced our jury.

Embedded Hardware at embedded world Exhibition&Conference Hardware is the basis for every embedded system

Wireless devices, IoT sensors and truly ultra-low power microprocessors 


Exhibitor: AntennaWare
Hall/Booth: 3/3-109

The human body is one of the most challenging environments for wireless devices due to the significantly reduced performance quality caused by, issues related to detuning and reduced coverage caused by body blocking. Body blocking is a key technical bottleneck in the adoption of wireless technology and occurs when there is no direct line of sight between the wearable device and the receiver as the human body blocks the propagation of the radio waves causing unreliable connections, reduced communication ranges and dropouts.


This has been a primary challenge for wireless wearables for over two decades. Although solutions try to mitigate against this problem, each solution introduces one or more of the following:

  • Increased transmit power
  • Increased circuit complexity
  • Shorter battery life/larger batteries
  • Increased surrounding wireless infrastructure
  • Additional BoM cost BodyWave™ antennas solve this problem by generating waves that flow efficiently round the body resulting in unprecedented performance at a range of frequencies including 1.9GHz, 2.4GHz and UWB.

The issue of body blocking and resulting unreliability of wireless wearable connections has restricted the adoption of wireless technology in many sectors, including healthcare and audio where there is low tolerance for dropouts. The proliferation of wireless technology & frequency band congestion, is forcing developers of wireless devices to move up in frequency where the effect of body blocking becomes greater.

AntennaWare’s patented BodyWave™ antenna range generates a novel form of propagation radio wave creating a bodywave that flows efficiently around the body, therefore supporting a communication link even when the body is blocking the signal i.e. non line of sight scenarios and solving the problem of body blocking for developers of wireless wearable devices. Built on 20 years of leading global research by Co-Founders Dr Matthew Magill and Dr Gareth Conway, BodyWave™ is the only commercially available antenna specifically designed for wearable applications, achieving a disruptive step-change of 10-20dB increased link budget in directions normally obscured by the human body when compared to existing commercially available chip and pin antennas.

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Apollo510 MCU

Apollo510 MCU

Exhibitor: Ambiq
Hall/Booth: 3/3-301


AI has been restricted to the Cloud as it requires huge volumes of data, compute, and performance for its intensive calculations. There are tremendous benefits in offering AI on devices for consumers to use 24/7, such as gaining insights into their health via their smartwatches or asking their virtual assistants on smart speakers for help. Factories and agriculture industries can leverage smart devices like motion detectors and location trackers to help drive efficiency and productivity.

How to enable AI on everything and everywhere has been Ambiq's mission for the last 14 years. In a highly competitive semiconductor industry, Ambiq has carved out a unique existence in delivering truly ultra-low power microprocessors with unprecedented energy efficiency and compute performance that drive the latest endpoint devices, including digital health devices, factory automation, agriculture, smart homes, and 75% of the global wearable products.

Reducing cloud dependence has four major benefits for AI on endpoint devices: power savings, privacy protection, latency reduction, and increased robustness. These benefits offer immense value for manufacturers and consumers, and the debut of Ambiq’s Apollo510 MCU is set to further this vision of enabling intelligent devices everywhere.

Ambiq's Apollo510 MCU was purpose-built to create more capable endpoint devices that enable AI. The Apollo510 uses subthreshold technology to perform AI at lower power consumption levels than previously thought possible. This incredible reduction in power consumption allows endpoint device manufacturers to dramatically expand their devices capabilities, reducing dependence on the cloud. They can add intensive and complex features such as AI that sips power versus drains.

The Apollo510 upgrades its hardware from previous generations furthering its energy optimization per compute cycle. It uses the Arm-Cortex M55 with Helium to achieve better latency and power consumption. For perspective, an AI benchmark test demonstrated 22X better efficiency than the already best-in-class Ambiq Apollo4, and a nearly 300x improvement over typical Cortex-M4 devices. This makes the Apollo510 the most energy efficient use case for the Arm-Cortex M55 on the planet. This combination of performance and efficiency will allow our customers to deploy sophisticated speech, vision, health, and industrial AI models on battery-powered devices everywhere, marking the start of the age of truly ubiquitous, practical and useful AI.

NASP Neuromorphic Front End Chip

NASP Neuromorphic Front End Chip

Exhibitor: POLYN Technology
Hall/Booth: 2/2-152


In recent years, IoT sensors are deployed extensively across various industries, collecting data for real-time monitoring. There is a growing trend towards wireless sensors using the advantages of cellular and NB communications, since wired sensor network installations are expensive and often technically impossible. However, for wireless sensors transmitting all the raw data demands broadband communication channels, resulting in significant energy use. There is a need to implement data pre-processing locally at sensor level with minimal power consumption, allowing the utilization of narrowband energy-efficient radio channels.

AI models suit best for dealing with non-linear data tasks. Additionally, some of the data collected can be sensitive and must remain at the edge with limited computing capacity. Therefore, Edge AI is assuming greater importance and edge devices are driving the demand for new energy-efficient AI processors.

The NASP NFE chip is based on the novel Neuromorphic Analog Signal Processing technology. The chip is intended to be placed directly after the sensor, to perform raw data pre-processing. The NASP NFE chip extracts from the sensor raw data only useful information reducing the data flow sent further by more than 1000 times, eliminating multiple subsequent costs associated with transmission, processing, and storage, reducing TCO and making the whole solution sustainable. The NASP NFE chip is designed with neuroscience in mind, replicating sensory data pre-processing that the primary cortical area of the human brain makes at the periphery before classification and learning in the central brain parts. Like human biological systems, the NASP NFE chips are application specific for processing voice, vibration, or other signals.

Data processing by NASP employs artificial neurons (nodes performing computations) and axons (connections with weights between the nodes) implemented using circuitry elements; neurons are implemented using operational amplifiers and axons using thin-film resistors built on top of the analog CMOS circuitry in BEOL. This approach provides 100% circuit area utilization per specific application. The chip design embodies the approach of a sparse neural network, with only the necessary connections between neurons required for inference. The analog design gives the NASP NFE such properties as ultra-low power consumption at about 100 microwatts and low inference latency at about few microsec.

Each application-specific chip is designed with the NASP T-Compiler and EDA tools. These unique tools convert a trained neural network into a math model for further chip layout generation, preserving absolute compliance with the initial neural network. This automation innovation addresses several challenges: converting a neural network into chip instead of adapting the network to a chip architecture and achieving development speed and ease.