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26 - 28 February 2019 // Nuremberg, Germany

Conferences and supporting programme

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Session 12 - FPGA based Hardware Solutions

Hardware Deceleration: The Challenges of Speeding Up Software Vortragssprache Englisch

Developing a custom ASIC, or designing for an SoC FPGA, gives us the potential to create very specific accelerators to speed up software bottlenecks. However, this is not without its challenges! How do you account for cached data and translation from virtual to physical addresses when moving data payloads from user space into the hardware? Moving data from the SoC FPGA to the Accelerator and back, has the potential of a lot of software overhead before work-loads can be started. In this presentation, Kris Chaplin will discuss techniques and mechanisms to allow hardware accelerators to actually accelerate, rather than slow down, a system (even accounting for the potential overhead required).

--- Date: 28.02.2018 Time: 4:30 PM - 5:30 PM Location: Conference Counter NCC Ost



Kris Chaplin

Intel Corporation


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