Conferences and supporting programme
Design Space Exploration for Convolutional Neural Networks on a 22nm FD-SOI SoC
Convolutional Neural Networks are increasingly used for Computer Vision tasks, including image classification, object detection and semantic segmentation. Following an offline training process, the trained models are used for inference on mobile platforms, as smartphones or cars. Hard requirements concerning the latency and throughput are in contradiction to the limited power budget and passive heat dissipation. Dream Chip Technologies GmbH has developed within the European funded THINGS2DO project a heterogeneous System-on-Chip in modern 22-nm FD-SOI technology. Besides an ARM Cortex-A53 Quadcore-Cluster, an ARM Cortex-R5 safety coprocessor, as well as image processing computing horsepower in the shape of four Tensilica Vision P6 DSPs is integrated. In this paper, we explore the design space for various convolutional neural networks performed on the described System-on-Chip. In-depth analysis of latency and throughput for different machine learning layers are presented in conjunction with the power consumption on the different processing architectures. Therefore, we inspect various design configurations, defined by the layer type, data format, number of parameters, kernel size and more design variables. The dependencies between algorithmic parameter configurations and corresponding physical results are modeled in a mathematical way. As a result, the performance and power consumption of the platform for a given network can be estimated, without implementing it.
--- Date: 28.02.2019 Time: 10:00 - 10:30 Location: Conference Counter NCC Ost