RISC-V is a new open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted.
As a member of the RISC-V Foundation, UltraSoC is deeply involved in developing and defining the debug architecture for RISC-V standards. UltraSoC fully supports both standards-based and proprietary debug approaches. We were the first company to offer a RISC-V processor trace solution, supporting both open source and commercial processors including those from Andes, Codasip, Microchip, Roa Logic, SiFive and Syntacore.
UltraSoC donates RISC-V trace implementation to enable true open-source development
Works through OpenHW Group to support design innovation and ensure ecosystem compatibility
UltraSoC has announced it will offer an open-source implementation of its industry-leading RISC-V trace encoder via the OpenHW Group. The availability of a production-grade, standards-compliant processor trace solution is a key enabler for developers, and supports the OpenHW Group’s aim of creating an open, commercial grade ecosystem for development based on open-source processors.