riscvOVPsim - RISC-V Instruction Set Simulator (ISS) - fast, simple, easy to use, cross software development for embedded systems
The riscvOVPsim ISS is an ideal starting point for an embedded software development project.
riscvOVPsim allows the development and debug of code for the target RISC-V processor on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running riscvOVPsim with an argument to specify the name of the application object.
Used by application software engineers who need to create software binaries for RISC-V permitted configurations and variants, but who do not need platform components - riscvOVPsim works with a standard GDB debugger and GUI which makes it very easy to get started with full source code interactive debugging.
Middleware library developers can also use riscvOVPsim when building software libraries for common functions, for example multimedia standards where they code at the assembly level and make extensive use of the processor data path - the debugger/GUI shows detailed assembly and all processor registers.
Test engineers can use riscvOVPsim in a regression test environment as it can be used in batch/scripted environments as well as being used interactively.
riscvOVPsim is also used by the RISC-V Foundation's Compliance working group in the RISC-V compliance test suite and framework, the latest version is available on GitHub: https://www.github.com/riscv/riscv-compliance
riscvOVPsim makes use of the Imperas OVP Fast Processor Model library for RISC-V single core instruction accurate configurations and variants.
Speeds of up to 1,000 MIPS can be expected on modern desktop PCs.