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15 - 17 March 2022 // Nuremberg, Germany

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Exhibitors & Products embedded world 2020
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GateMate FPGA


GateMate FPGA

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Overview of GateMateTM FPGA

The GateMateTM FPGA family of Cologne ChipTM AG is based on a novel FPGA architecture combining a special logic element called Cologne Programmable Element (CPE) with a smart routing engine. Furthermore, arbitrary size multipliers are usable. Memory aware applications can use block RAMs with bit widths of 1 to 80 bits. Even bit-wise enable is possible.
General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volt. GPIOs can be configured as single-ended or LVDS differential type. Furthermore a high speed SERDES interface is available.

GateMateTM FPGAs are supported by the software EasyConvertTM, that enables the transfer of existing FPGA designs without new synthesis. Worldclass P&R-software maps and implements the design into GateMateTM FPGA. A Static Timing Analysis (STA) is also performed and gives evidence about critical pathes and the overall performance of a design. The design can be easily simulated using Verilog netlist and SDF timing extraction. The devices are manufactured using GlobalfoundriesTM 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high customs.

Technical features of GateMateTM FPGA

•    Logic capacity from 40.000 to more than a million LUT-4 equivalent cells
•    Novel architecture with new programmable element (CPE)
•    CPE consists of LUT-tree with 8 inputs
•    3 operation areas: low power, economy, speed         
•    FPGA in ball grid package for low size and high pin count
•    Only 2 signal layers on PCB necessary
•    Low configuration bit count
•    Very fast configuration using 4 bit SPI interface up to 100 MHz
•    No excessive start-up currents
•    Only two supply voltages needed, that can be applied in any order
•    Multiple clocking schemas
•    Dual ported Block RAMs with 20-80 bit data width, also configurable as FIFO
•    Multipliers with arbitrary factor width implementable
•    SERDES 2.5 Gb/s
•    General Purpose IOs (GPIO) configurable as single-ended or differential
•    Pullup/Pulldown resistors configurable
•    Support for ADC and DAC with additional IP cores
•    Core voltage depending on application mode: 0.9 V, 1.0 V, 1.1 V
•    Low Power 28 nm SLP GlobalfoundriesTM process technology
•    Made in Europe
•    EasyConvertTM software to migrate existing designs to GateMateTM
•    GateMateTM Place&Route with automatic clock Skew analysis and fixing
•    Static Timing Analysis for performance evaluation

GateMateTM FPGA is available in different sizes:

  1. CCGM1A1: 20,480 CPEs | 20,480 8-Inp-LUTtree | 40,960 FF/Latches | 4 PLLs | 1 SERDES | 320 BGA Balls | 15x15 mm
  2. CCGM1A2: 40,960 CPEs | 40,960 8-Inp-LUTtree | 81,920 FF/Latches | 8 PLLs | 2 SERDES | 320 BGA Balls | 15x15 mm
  3. CCGM1A4: 81,920 CPEs | 81,920 8-Inp-LUTtree | 163,840 FF/Latches | 16 PLLs | 4 SERDES | 320 BGA Balls | 15x15 m  
  4. CCGM1A9: 184,320 CPEs | 184,320 8-Inp-LUTtree | 368,640 FF/Latches | 36 PLLs | 9 SERDES   
  5. CCGM1A16: 327,680 CPEs | 327,680 8-Inp-LUTtree | 655,360 FF/Latches | 64 PLLs | 16 SERDES     

CCGM1A25: 512,000 CPEs | 512,000 8-Inp-LUTtree | 1,024,000 FF/Latches | 100 PLLs | 25 SERDES

GateMate FPGA is assigned to following product groups:


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