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2 - 4 March 2021 // Nuremberg, Germany

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Exhibitors & Products embedded world 2020
Zoom Image LOGO_Timing Analysis for Real-Time Software

Timing Analysis for Real-Time Software

LOGO_Timing Analysis for Real-Time Software

Timing Analysis for Real-Time Software

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In real-time systems, timely task completion is of the essence. Each real-time task has to be completed within a specified time frame in order to ensure that the system works correctly. In other words, it is essential that the worst-case execution time (WCET) of each task is known.

AbsInt provides three different tools for WCET analysis which are tailored to three different use cases. All of them support batch mode execution and integration in continuous integration frameworks.

aiT WCET Analyzer - Static WCET Guarantees

aiT statically computes tight upper bounds for the worst-case execution time of tasks on timing-predictable single-core and multicore processors. aiT directly analyzes binary executables and takes the intrinsic cache and pipeline behavior into account.

aiT is based on the technique of abstract interpretation, a formal methodology for semantics-based static analysis, which can provide soundness guarantees: the WCET bounds will never be exceeded by any possible program execution.

A graphical user interface supports the visualization of the worst-case program path and the interactive inspection of all pipeline and cache states at arbitrary program points.

aiT is available for a variety of microprocessors ranging from simple processors like ARM7 to complex superscalar processors like Freescale MPC755, or MPC7448, and multicore processors like Freescale MPC 5777M, and Infineon AURIX TC27x.

TimeWeaver - Non-Intrusive Hybrid WCET Analysis

TimeWeaver combines static path analysis with real-time instruction-level tracing to provide worst-case execution time estimates. The computed time bounds provide valuable feedback for assessing system safety and for optimizing worst-case performance. It supports many modern high-performance processors, e.g. all PowerPC boards providing Nexus program trace messages (IEEE-ISTO 5001, class 2 or higher), or ARM using cycle-accurate ETM traces.

TimeWeaver analyses all potential execution paths and computes the longest path based on the execution times of trace segments observed in real-time traces. The trace information covers interference effects, e.g., by accesses to shared resources from different cores, without being distorted by probe effects since no instrumentation code is needed. The computed time bounds are compliant to requirements of safety standards like ISO-26262.

The analysis results include the computed WCET bound with the time-critical path, and information about the trace coverage obtained. They provide valuable feedback for optimizing trace coverage, for assessing system safety, and for optimizing worst-case performance.

TimingProfiler - Zero-Overhead WCET Estimation in Early Design Stages

TimingProfiler helps developers identify application parts that are causing unsatisfactory execution times. It is ideally suited for constantly monitoring timing behavior during software development and in model-based development environments. TimingProfiler delivers results as soon as there is compiled code. It can be used early in the process when measurements on physical hardware are costly or not even possible. The analysis is purely static. No access to physical hardware and no code instrumentation are required.

TimingProfiler takes executable code as input and explores the timing of all potential execution paths of each task on a generic processor with the target instruction set, e.g. PowerPC. No user interaction is required; information not statically available is filled in by specialized heuristics. Hence, the resulting execution time is a realistic worst-case scenario, albeit not a guarantee as provided by aiT.

TimingProfiler gives detailed information about the execution time and time-critical paths. The tool shows call and control flow graphs, and displays all relevant information about the executable. Hotspots and bottlenecks can be identified at early development stages so that late-stage integration problems can be avoided.


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