Cologne Chip AG

Eintrachtstraße 113

50668 Köln

Nordrhein-Westfalen

Germany

Phone: +49(0)221.9124-0

Fax: +49(0)221.9124-100

www.colognechip.com

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Hall 3 / 3-446

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Cologne Chip^TM AG is a semiconductor manufacturer that offers telecommunications ICs and intellectual property (IP) as well as FPGAs since this year. The GateMate^TM FPGA family sets the standard for small to mid-size FPGAs. The programmable silicon can be used in low-power and speed applications and is therefore suitable for a variety of applications: industry, automation, communications, security, automotive, IoT, lighting etc.
Logic capacity, power consumption, package size and PCB compatibility are best in class. GateMate^TM FPGAs combine these features with lowest cost in industry making the devices well suited from University projects to high volume applications. Because of the outstanding ratio of circuit size to cost, even price-sensitive applications now can also take advantage of FPGAs.
Since Cologne Chip^TM AG can look back on a company history of more than 25 years, its customers benefit with GateMate^TM FPGAs from an excellent industry knowledge, an experienced team and a design and manufacturing location "Made in Germany". GateMate^TM FPGAs are funded by the German Federal Ministry of Economics and Energy.

GateMate FPGA

Overview of GateMate^TM FPGA

The GateMate^TM FPGA family of Cologne Chip^TM AG is based on a novel FPGA architecture combining a special logic element called Cologne Programmable Element (CPE) with a smart routing engine. Furthermore, arbitrary size multipliers are usable. Memory aware applications can use block RAMs with bit widths of 1 to 80 bits. Even bit-wise enable is possible.
General Purpose IOs (GPIOs) can use different voltage levels from 1.2 to 2.5 Volt. GPIOs can be configured as single-ended or LVDS differential type. Furthermore a high speed SERDES interface is available.

GateMate^TM FPGAs are supported by the software EasyConvert^TM, that enables the transfer of existing FPGA designs without new synthesis. Worldclass P&R-software maps and implements the design into GateMate^TM FPGA. A Static Timing Analysis (STA) is also performed and gives evidence about critical pathes and the overall performance of a design. The design can be easily simulated using Verilog netlist and SDF timing extraction. The devices are manufactured using Globalfoundries^TM 28 nm SLP (Super Low Power) process. Due to manufacturing in Europe, there is no danger of trade restrictions or high customs.

Technical features of GateMate^TM FPGA

•   Logic capacity from 40.000 to more than a million LUT-4 equivalent cells
•   Novel architecture with new programmable element (CPE)
•   CPE consists of LUT-tree with 8 inputs
•   3 operation areas: low power, economy, speed
•   FPGA in ball grid package for low size and high pin count
•   Only 2 signal layers on PCB necessary
•   Low configuration bit count
•   Very fast configuration using 4 bit SPI interface up to 100 MHz
•   No excessive start-up currents
•   Only two supply voltages needed, that can be applied in any order
•   Multiple clocking schemas
•   Dual ported Block RAMs with 20-80 bit data width, also configurable as FIFO
•   Multipliers with arbitrary factor width implementable
•   SERDES 2.5 Gb/s
•   General Purpose IOs (GPIO) configurable as single-ended or differential
•   Pullup/Pulldown resistors configurable
•   Support for ADC and DAC with additional IP cores
•   Core voltage depending on application mode: 0.9 V, 1.0 V, 1.1 V
•   Low Power 28 nm SLP GlobalfoundriesTM process technology
•   Made in Europe
•   EasyConvert^TM software to migrate existing designs to GateMateTM
•   GateMate^TM Place&Route with automatic clock Skew analysis and fixing
•   Static Timing Analysis for performance evaluation

GateMate^TM FPGA is available in different sizes:

CCGM1A1: 20,480 CPEs | 20,480 8-Inp-LUTtree | 40,960 FF/Latches | 4 PLLs | 1 SERDES | 320 BGA Balls | 15x15 mm
CCGM1A2: 40,960 CPEs | 40,960 8-Inp-LUTtree | 81,920 FF/Latches | 8 PLLs | 2 SERDES | 320 BGA Balls | 15x15 mm
CCGM1A4: 81,920 CPEs | 81,920 8-Inp-LUTtree | 163,840 FF/Latches | 16 PLLs | 4 SERDES | 320 BGA Balls | 15x15 m
CCGM1A9: 184,320 CPEs | 184,320 8-Inp-LUTtree | 368,640 FF/Latches | 36 PLLs | 9 SERDES
CCGM1A16: 327,680 CPEs | 327,680 8-Inp-LUTtree | 655,360 FF/Latches | 64 PLLs | 16 SERDES

CCGM1A25: 512,000 CPEs | 512,000 8-Inp-LUTtree | 1,024,000 FF/Latches | 100 PLLs | 25 SERDES