Cortus S.A.S.

The APS1 is the smallest available 32-bit processor IP core. The APS1 requires a tiny silicon footprint and consumes very little power. It is suitable for deeply-embedded applications with smaller code and data memory requirements.

The APS1 CPU starts at about 7.1 kgates meaning that its silicon footprint is smaller than some 8-bit cores. However, the APS1 brings the benefit of much more straightforward SW development using C or C++. Code density is better than with 8-bit cores meaning that the code memory requires a smaller silicon area. With both a small silicon area and reasonable computational performance, the core consumes very little dynamic or static power.

The core is supported with peripherals, bridges, software development tools and real time operating systems.

The APS1 is the natural choice for upgrading 8-bit embedded SoC applications to 32-bits to reduce power and improve SW development time.

Features

• 32 bit modern RISC architecture
• Designed for C/C++
• 16 registers
• Up to 27 interrupts
• From 7.1 kgates
• 3-stage pipeline
• 64 KB data memory addressing
• 64 KB code memory addressing
• 2.37 DMIPS/MHz
• 0.32 CoreMarks/MHz
• Max clock frequency: 307 MHz, 90 nm
• Dynamic power: 10 µW/MHz, 90 nm
• Standard peripherals (timers, counters, I2C, SPI, UART, GPIO, etc)
• Ethernet 10/100, USB 2.0 and USB OTG peripherals
• Latency free interface to and from AHB Lite and to APB
• Eclipse-based IDE
• Ports of FreeRTOS, OpenRTOS, Micrium µC/OSII & III and TargetOS

Applications

• RFID
• Near field communication (NFC)
• Wireless sensor networks
• Touch screen controllers for tablet computers and smartphones
• Sensor control
• Automotive sensors
• Programmable state machines
• Lightweight wireless protocols

The APS25 32-bit processor core IP is aimed at high performance embedded system-on-chip (SoC) applications. The APS25 supports the creation of more complex processor subsystems with caches, coprocessors and multiple cores.

The APS25 CPU starts at around 19 kgates and includes a parallel multiplier and HW divider. The core design is optimised for high throughput and is capable of over 400 MHz with 90 nm geometries. The APS25 can be used in single-, dual- or multi-core configurations or in heterogeneous systems with other APS cores. The core supports the AXI4-Lite bus.

The core is supported with peripherals, bridges, software development tools and real time operating systems.

The APS25 is the natural choice for embedded applications that require good integer performance.

Features

• 32-bit modern RISC architecture
• Designed for C/C++
• 16 registers
• Up to 256 interrupts with up to 16 priority levels
• From 18.8 kgates
• 5-stage pipeline
• 4 GB addressing
• 2.28 DMIPS/MHz
• 2.52 CoreMarks/MHz
• Max clock frequency: 400 MHz, 90 nm
• Dynamic power: 19 µW/MHz, 90 nm
• AXI4-Lite bus
• Standard peripherals (timers, counters, I2C, SPI, UART, GPIO, etc)
• Ethernet 10/100, USB 2.0 and USB OTG peripherals
• Optional instruction and data caches
• Co-processor interface
• Latency free interface to and from AHB Lite and to APB
• Elipse-based IDE
• Ports of FreeRTOS, OpenRTOS, Micrium µC/OSII® & µC/OSIII®, TargetOS and µC Linux

Applications

• Advanced sensing applications
• Dual- and multi-core systems
• Encryption/decryption
• Home automation
• Wireless communication
• Wireline communication
• Embedded control

The APS3R 32 bit processor IP core is aimed at embedded system on chip (SoC) applications. The APS3R combines silicon efficiency with good computational performance yielding outstanding dynamic and static power consumption.

The APS3R CPU starts at about 7.8 kgates meaning that its silicon footprint is comparable to 8-bit cores such as the 8051. However, the APS3R brings the benefit of much more straightforward SW development using C or C++. Code density is better than with 8-bit or 16-bit cores meaning that the code memory requires a smaller silicon area. With both a small silicon area and good computational performance, the core consumes very little dynamic or static power.

The core is supported with peripherals, bridges, software development tools and real time operating systems.

The APS3R is the smart choice for embedded security and wireless applications.

Features

• 32-bit modern RISC architecture
• Designed for C/C++
• 16 registers
• Up to 256 interrupts with up to 16 priority levels
• From 7.8 kgates
• 3-stage pipeline
• 4 GB addressing (code and data)
• 2.76 DMIPS/MHz
• 1.52 CoreMarks/MHz
• Max clock frequency: 312 MHz, 90 nm
• Dynamic power: 12 µW/MHz, 90 nm
• Standard peripherals (timers, counters, I2C, SPI, UART, GPIO, etc)
• Ethernet 10/100, USB 2.0 and USB OTG peripherals
• Latency free interface to and from AHB Lite and to APB
• Eclipse-based IDE
• Ports of FreeRTOS, OpenRTOS, Micrium µC/OSII & III, TargetOS and µC Linux

Applications

• IoT edge devices
• SIM cards
• Smart cards
• Bluetooth (Classic and LE)
• Wi-Fi
• Near field communication (NFC)
• Wireless sensor networks
• Home networking
• Smart metering
• Touch screen controllers for tablet computers and smartphones
• Sensor control
• Medical monitoring devices
• Image processing
• Automotive sensing
• Domestic appliances

The Cortus Development Platform is an ideal tool for evaluating and prototyping the full range of Cortus APS 32-bit processors and multi-core systems.  It features a Xilinx Spartan®-6 X75 which is large enough to prototype substantial single and multicore systems based around Cortus processors.

1 Mbyte of high speed synchronous static RAM is available for application use, giving single cycle access for systems running at up to 100 MHz. A 32 Mbit serial (SPI) Flash memory holds the FPGA configuration and can be shared to hold the application software. A USB interface assures the JTAG connection (Windows and Linux drivers are available) which is fully compatible with Cortus tools. A second channel (over the same USB interface) provides a UART connection to the system being prototyped, ideal for terminal applications.

The FPGA board offers an I/O footprint that is compatible with the Arduino Due enabling the use of shields designed for that platform. Additional I/O connectors are available to extend the memory available to the platform with DDR2 memory to 512 Mbytes. This gives enough memory to run a complete version of Linux on the board. Additionally this memory extension can include a USB2.0 PHY to combine with the Cortus USB2.0 MAC creating an ideal platform for prototyping embedded Linux systems.

The platform is fully integrated with the Cortus IDE, Cortus toolchain and software development tools and also IDEs from Cortus’ partners.

Features

• Spartan®-6 X76
• 1 Mbyte synchronous SRAM
• 32 Mbit SPI flash
• 10/100 Mbits/s Ethernet PHY
• FT2232H for JTAG and serial
• Arduino Due I/O connector footprint
• 50 MHz clock oscillator

Applications

• Prototyping ASICs/SoCs using Cortus APS cores
• Software development for Cortus APS cores
• Evaluation of Cortus APS cores

The FPS26 32-bit processor core IP is aimed at high performance embedded system-on-chip (SoC) applications such as motor control, power control, MIMO baseband processing, complex gesture recognition or solar inverters. The FPS6 is optimised for efficient floating point and integer computation.

The FPS26 CPU starts at around 35 kgates which is considerably smaller than most other floating point microcontrollers. The core design is optimised for high throughput and is capable of over 350 MHz with 90 nm geometries. The FPS26 offers 30.2 MFLOPS (single precision Linpack benchmark) at 333 MHz. The FPS26 can be used in dual- or multi-core configurations or in heterogeneous systems with other APS cores. The core supports the AXI4-Lite bus.

The core is supported with peripherals, bridges, software development tools and real time operating systems.

The FPS26 is the smart choice for embedded applications that require good floating point performance.

Features

• 32-bit modern RISC architecture
• Single precision IEEE floating point
• Designed for C/C++
• 16 registers
• Up to 256 interrupts with up to 16 priority levels
• From 35 kgates
• 4 GB addressing
• 2.28 DMIPS/MHz
• 2.52 CoreMarks/MHz
• 30.2 MFLOPS (Linpack) @ 333 MHz
• AXI4-Lite Bus
• Max clock frequency: 392 MHz, 90 nm
• Dynamic power: 37 µW/MHz, 90 nm
• Standard peripherals (timers, counters, I2C, SPI, UART, GPIO, etc)
• Ethernet 10/100, USB 2.0 and USB OTG peripherals
• Optional instruction and data caches
• Latency free interface to and from AHB Lite and to APB
• Eclipse-based IDE
• Ports of FreeRTOS, OpenRTOS, Micrium µC/OS and µC Linux

Applications

• Industrial automation
• Motor control
• Advanced sensing applications
• MIMO baseband processing
• Advanced gesture recognition for man machine interface
• Energy management
• Smart Grid applications