The RISC-V Processor Developer Suite contains the models and tools necessary to validate and verify the functionality of a RISC-V processor. It also enables the early estimation of timing performance and power consumption for the processor.
Processor developers need models and tools to achieve the objectives of conformance, functionality verification and performance estimation. Also, given the open nature of the RISC-V architecture, the models need to be easily extendable to accommodate changes as the specific processor evolves. These models and tools also need to work in larger platforms and environments, providing professional software development, debug and test solutions to the user community.
The Imperas RISC-V Processor Developer Suite delivers commercially supported models, the fastest software simulator and a suite of tools:
- Infrastructure to easily evaluate RISC-V conformance
- Reference models for design verification
- Standard software tool chains including compiler, linker, debugger, and Eclipse integration
- Fast Processor Models, Instruction Set Simulator (ISS) and extendable virtual platforms
- Processor model instruction code coverage and profiling
- Timing performance and power estimation tools
- Many test suites, with different goals, to measure and maintain processor quality
Imperas supports all RV64/32 permitted configurations and variants as well as models of Andes, SiFive and other popular RISC-V cores, and has Extendable Platform Kits (EPKs) of Microsemi RISC‑V based devices running FreeRTOS, all available from the Open Virtual Platforms (OVP) website. All RISC-V features are implemented in the models, which are easily extendable with user defined instructions, registers and accelerators.
For more information see: http://www..imperas.com/imperas-riscv-solutions
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