27 February - 1 March 2018 // Nuremberg, Germany

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Exhibitors & Products embedded world 2017


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The APS1 is the smallest available 32-bit processor IP core. The APS1 requires a tiny silicon footprint and consumes very little power. It is suitable for deeply-embedded applications with smaller code and data memory requirements.

The APS1 CPU starts at about 7.1 kgates meaning that its silicon footprint is smaller than some 8-bit cores. However, the APS1 brings the benefit of much more straightforward SW development using C or C++. Code density is better than with 8-bit cores meaning that the code memory requires a smaller silicon area. With both a small silicon area and reasonable computational performance, the core consumes very little dynamic or static power.

The core is supported with peripherals, bridges, software development tools and real time operating systems.

The APS1 is the natural choice for upgrading 8-bit embedded SoC applications to 32-bits to reduce power and improve SW development time.


  • 32 bit modern RISC architecture
  • Designed for C/C++
  • 16 registers
  • Up to 27 interrupts
  • From 7.1 kgates
  • 3-stage pipeline
  • 64 KB data memory addressing
  • 64 KB code memory addressing
  • 2.37 DMIPS/MHz
  • 0.32 CoreMarks/MHz
  • Max clock frequency: 307 MHz, 90 nm
  • Dynamic power: 10 µW/MHz, 90 nm
  • Standard peripherals (timers, counters, I2C, SPI, UART, GPIO, etc)
  • Ethernet 10/100, USB 2.0 and USB OTG peripherals
  • Latency free interface to and from AHB Lite and to APB
  • Eclipse-based IDE
  • Ports of FreeRTOS, OpenRTOS, Micrium µC/OSII & III and TargetOS


  • RFID
  • Near field communication (NFC)
  • Wireless sensor networks
  • Touch screen controllers for tablet computers and smartphones
  • Sensor control
  • Automotive sensors
  • Programmable state machines
  • Lightweight wireless protocols





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APS1 is assigned to following product groups:


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