Konferenzen und Rahmenprogramm
Test Automation for Reengineered Modules Using Test Description Language and FPGA
In an ongoing research project funded by the German ministry of economics and innovation, a test automaton is currently developed which supports the test of reengineered components. Reengineering of components is a need in systems where the system as a whole lives longer than its parts, e.g. digital system components of railway systems, power plants etc. become obsolete due to obsolete processors, digital devices etc. Moreover, due to the age of the components documents from requirement analysis and design are often no more accessible. On the other hand, modern FPGA technology gives the opportunity to integrate a lot of the old parts including the replacement of old processors by hardware emulations. Therefore, our project is focused around test automation in order to find a safe way by which old components (OCmp) may be replaced with reverse engineered ones (RCmp). The first step in the reengineering process is the observation and measurement of reactions to stimuli which are taken from the OCmp using typical measurement & test equipment. This leads to a series of stimuli-response files (e.g. VCD files) which specify test cases for the component. In a second step, the component is reverse engineered using a HDL and, if programmable, processor emulators etc. The third step is a systematical test: The stimuli and response files are used to validate a functional model of the RCmp e.g. with a HDL simulator and to validate the RCmp itself which is configured onto the FPGA device. To implement systematic and well documented tests, our project defines a test description language (TDL) based on the ETSI ES 203 119-1 standard and a test automaton. The TDL is designed in accordance with the ETSI TDL standard as a domain specific language which facilitates writing a language sensitive editor as well as code generators. It is used as follows: The stimuli and response test cases are transformed into the TDL form. Subsequently, they are used to generate a VCD stimuli file as well as a VHDL testbench. The test automaton contains a test engine which connects to a control computer, generates the stimuli for the RCmp and captures its reactions. Additionally it contains signal adapter cards converting analog to digital signals according to the components interfaces as well as adapting the test engines signals to diverse signal levels. During Tests, the stimuli are loaded into our test automaton which is connected either to the OCmp or the RCmp. The generated VHDL testbench is used to compare the test results of the simulated and measured RCmp. The produced test report contains the results of the test with the OCmp or RCmp. The development of our automated test system has been done in close connection with the German attestation organization ‘TÜV’. This makes us confident that we will be able to use it in a SIL 3 reengineering case: the reengineering of a slide protection system (ABS) in a city railway.
--- Datum: 28.02.2018 Uhrzeit: 15:00 Uhr - 15:30 Uhr Ort: Conference Counter NCC Ost