Konferenzen und Rahmenprogramm
Low-bit CNN Implementation and Optimization on FPGA
Currently, AI applications demands for large models with huge MAC operations. In order to deploy such applications with a practical performance, powerful hardware is often needed, which will also consume more power. This paper proposes a new FPGA design using low bit quantization technique which uses 4 bit for both weights and activations, but can still keep accuracy of original neural network. Such low bit CNN design can achieve significant performance boosting and higher power efficiency. Our paper will use OpenPose algorithm as the demonstration for AI application, which is popular in pedestrain detection and the model is large enough. With our low bit CNN design, and optimized post-processing for OpenPose algorithm, we can see more smooth pedestrain detection application compared to original design.
--- Datum: 26.02.2020 Uhrzeit: 15:00 - 15:30 Uhr Ort: Conference Counter NCC Ost