Conferences and supporting programme
Virtual Platform Environment for the Bring Up and Test of a Secure Many-Core RTOS
The increasing numbers of cores in the individual SoCs, the move to multiple SoCs in Electronic Control Units (ECUs) and the increase in complexity of software for automotive electronics has led to the need for many-core support for real time operating systems (RTOSs). In addition, security requirements on the systems are directly flowed down to security requirements on the RTOS. With this increasing complexity of hardware, software and security requirements, the challenge to bring up and test the RTOS and basic software (BSW) has become much difficult. This paper reports on the use of a virtual platform (software simulation) based environment for the bring up and testing of a secure, many-core RTOS on an ECU. The RTOS is the eMCOS RTOS from eSOL, the hardware represented in the virtual platform is two Renesas RH850F1H devices (SoCs), and the virtual platform tools are from Imperas. The RH850F1H devices include a two separate RH850G3M processors and assorted peripheral components. For this project, instruction accurate models of the RH850F1H devices were built, using the RH850G3 Fast Processor Model from the Open Virtual Platforms (OVP) Library, and using the OVP APIs to build the peripheral models and the virtual platform. Two instances of the RH850F1H, connected via a UART, were implemented in the virtual platform to represent the ECU. The eMCOS RTOS uses a distributed microkernel architecture that is different from any existing single-core or multi-core RTOS. This enables it to make the best use of many-core processor hardware, because it does not depend on cache coherency mechanisms. eMCOS also uses the MPUs in the target hardware to allow users to designate secure memory regions. This paper will describe the process of building the virtual platform models, and the bring up and testing of eMCOS. Productivity tools which help with port and register definitions for the peripheral models, and with memory, buses, connectivity, and hierarchy for the platform, have been developed. Overall simulation performance of about 200 million instructions per second (MIPS) was achieved, or about 50 MIPS per core. The method and tools used for multi-processor debug, taking a platform-centric instead of the usual processor-centric approach to debug, will be described. The methods and specific tools, such as parameterized memory monitors, for testing adherence to the security requirements are presented. Also, non-intrusive OS-aware tools have greatly increased the OS bring up process. The architecture of the simulation environment, enabling support of a new RTOS with about 1 week of engineering effort, and enabling non-intrusive tools, will be presented.
--- Date: 28.02.2018 Time: 4:30 PM - 5:00 PM Location: Conference Counter NCC Ost