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25 - 27 February 2020 // Nuremberg, Germany

Conferences and supporting programme

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Session 5.3: RISC-V III System

User Mode Interrupts: A Must for Securing Embedded Systems Vortragssprache Englisch

All modern processor architectures define some levels of privilege to support secure system design. However, servicing interrupts with high privileged code completely breaks the security model. So, what should a security-conscious designer do? Is a system really secure if interrupts aren’t secure? Real time operating systems, runtime frameworks, peripheral drivers, 3rd party libraries: they all have interrupts handlers that are not verified or proprietary - which likely means not verifiable. How do you build a trusted computing model when potentially untrusted code has high privilege access through its interrupt handlers? In this workshop, industry veteran Cesare Garlati - Chief Security Strategist at the non-profit prpl Foundation, uncovers the problem of securing interrupts in embedded systems and introduces an innovative approach to interrupt security that doesn’t require specific hardware extensions. Robust solutions to interrupt security are presented for three different scenarios: traditional monolithic code base, dual-world implementation - similar to ARM’s TrustZone, and a multi-domain trusted execution environment. This workshop is a must-attend for system designer and embedded developers who understand the risk of unsecured interrupt handlers but can’t afford to switch to a platform that provides built-in support or extensions for user-mode interrupts.

--- Date: 26.02.2019 Time: 4:00 PM - 4:30 PM Location: Conference Counter NCC Ost



Prof. Sandro Pinto

Universidade do Minho

 Cesare Garlati

Cesare Garlati

Chief Strategist and Member RISC-V / prpl Foundation


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