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25 - 27 February 2020 // Nuremberg, Germany

Conferences and supporting programme

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Session 5.1: RISC-V I Overview

The Soul of a New SoC: Hands-on Experience with Embedding a RISC-V Core Vortragssprache Englisch

RISC-V is an open instruction set architecture which is increasingly gaining interest in the research & open-source community and offers a lot of advantages. With a RISC-V ISA implementation, designers can develop their own processor system and maintain production of developed parts over process or PLD lifetimes as RTL sources can be easily transferred. Moreover, RISC-V offers a lot of optimization options like implementation of custom instructions and scalable architectures. The RISC-V ISA is competing with ARM, especially in low volume industrial applications. With the embedding of a processor into a mixed signal IC for motor and motion control, highly integrated motor controllers can be designed. By doing so, the former motor driver is augmented to an intelligent and self-monitoring motor control solution. In this paper, the process of embedding a RISC-V core into a hardware design is described. The decision process and all greater implementation decisions are explained. Tradeoffs had to be made in several design areas, starting from the feature set of the core followed by its frequency and the additional clock domains. Chip size was mainly influenced by the size of NVM and SRAM. IP was bought to shorten development time. Analog circuitry enlarged the product to a unique product. Standard peripherals optimized for motion control make the product highly flexible. Practical learnings are presented as well as the developed product and the roadmap that came up during development.

--- Date: 26.02.2019 Time: 10:30 AM - 11:00 AM Location: Conference Counter NCC Ost



Onno Martens

TRINAMIC Motion Control GmbH & Co. KG


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