Conferences and supporting programme
RISC-V; the Software and Hardware Aspects of an Open Source ISA
RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley. In this talk we will look at some of the details of how the RISC-V architecture compares to other RISC based cores on the market, and look at some of the ecosystem around RISC-V including software development tools, security, vector extensions and debug. We will also look at some of the commercial support and applications deploying RISC-V and give an overview of where the technology is going.
--- Date: 01.03.2018 Time: 9:30 AM - 10:00 AM Location: Conference Counter NCC Ost