27 February - 1 March 2018 // Nuremberg, Germany

Conferences and supporting programme

back to day overview
Session 33 - Hardware: The Right Choice

RISC-V; the Software and Hardware Aspects of an Open Source ISA Vortragssprache Englisch

RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley. In this talk we will look at some of the details of how the RISC-V architecture compares to other RISC based cores on the market, and look at some of the ecosystem around RISC-V including software development tools, security, vector extensions and debug. We will also look at some of the commercial support and applications deploying RISC-V and give an overview of where the technology is going.

--- Date: 01.03.2018 Time: 9:30 AM - 10:00 AM Location: Conference Counter NCC Ost

Speakers

man

Prof. Robert Oshana

/ NXP Semiconductors Germany GmbH

top

The selected entry has been placed in your favourites!

If you register you can save your favourites permanently and access all entries even when underway – via laptop or tablet.

You can register an account here to save your settings in the Exhibitors and Products Database and as well as in the Supporting Programme.The registration is not for the TicketShop and ExhibitorShop.

Register now

Your advantages at a glance:

  • Advantage Save your favourites permanently. Use the instant access to exhibitors or products saved – mobile too, anytime and anywhere – incl. memo function.
  • Advantage The optional newsletter gives you regular up-to-date information about new exhibitors and products – matched to your interests.
  • Advantage Call up your favourites mobile too! Simply log in and access them at anytime.