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26 - 28 February 2019 // Nuremberg, Germany

Conferences and supporting programme

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Session 5.3: RISC-V III System

RISC-V Project in Western Digital: ... Vortragssprache Englisch

RISC-V Instruction Set Architecture has become a key driver for driving open source. Most recently we have seen a lot of application in the Internet of Things (IoT), microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of inference engines (AI) based on artificial neural networks. In Western Digital, we have developed super-scalar (2-way) 9-stage pipeline mostly in-order, open-source core ECHX1, initially targeting in-house embedded Storage System on Chip applications. In this paper, we plan to present some of the architectural details of the core, and challenges in the implementations, as well as discuss application of the core for the Flash controller. We will also show measurement of Coremark and Dhrystone benchmarks. Additionally, we will explain the vision for expansion of RISC-V cores into AI machine learning (ML) and AI workload acceleration – both for IoT and datacenter and enterprise market. We will explain the importance of free and open vector instruction extensions of RISC-V for these new AI related applications. We will present details of the Western digital machine learning accelerator platform, and show ResNet-50 benchmark results. We will also introduce MPF4brik memory protocol - exporting open cache-coherence protocols (such as Tilelink) over ubiquitous fabrics such as Ethernet. We will show typical latency measurements in such open symmetric multiprocessing) shared memory system.

--- Date: 26.02.2019 Time: 5:00 PM - 5:30 PM Location: Conference Counter NCC Ost



Dr. Zvonimir Bandic

Western Digital


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