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26 - 28 February 2019 // Nuremberg, Germany

Conferences and supporting programme

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Session 5.3: RISC-V III System

RISC-V: High Performance Embedded SweRV Core Microarchitecture, Performance and Implementation Challenges Vortragssprache Englisch

RISC-V: high performance embedded SweRV core microarchitecture, performance and implementation challengesRISC-V Instruction Set Architecture (ISA) has become a key driver of open source hardware projects. Most recently we have for example seen a lot of applications in the Internet of Things (IoT), microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of Artificial Intelligence (AI) inference engines based on artificial neural networks. We have developed a super-scalar (2-way), 9-stage pipeline, mostly in-order, open-source core based on the RISC-V RV32IMC instructions set, named SweRV. It initially targets in-house embedded Storage System on Chip applications. We present some of the architectural details of the core and implementation challenges, as well as discuss application of the core for the Flash controllers. We also report performance measurements of Coremark and Dhrystone benchmarks, which are traditionally used for embedded core performance benchmarking. In addition to the SweRV core, we have also developed a SweRV Instruction Set Simulator (ISS). We present some of the details of the simulator, including performance numbers. Some of the implementation challenges that we have encountered were related to the tradeoff of code density and performance of RISC-V. We report our initial findings and code density improvement solutions based on compiler and linker optimizations.

--- Date: 26.02.2019 Time: 5:00 PM - 5:30 PM Location: Conference Counter NCC Ost

Speakers

man

Dr. Zvonimir Bandic

Western Digital

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