Conferences and supporting programme
Partitioning of Computationally Intensive Tasks Between FPGA and CPUs
With the recent development of faster and more complex Multiprocessor System-on-Chips (MPSoCs), a large number of different resources are available on one chip. For example, Xilinx's Zynq UltraScale+ is a powerful MPSoC with four ARM Cortex-A53 CPUs, two Cortex-R5 real-time cores, an FPGA fabric and a Mali-400 GPU. Optimal process partitioning between CPUs, real-time cores, GPU and FPGA is therefore a challenge. For many scientific applications with high sampling rates and real-time signal analysis, an FFT needs to be calculated and analyzed directly in the measuring device. The goal of partitioning such an FFT on an MPSoC is to make best use of the available resources, to minimize latency and to optimize performance. The paper compares different partitioning designs and discusses their advantages and disadvantages. Measurement results with up to 250 MSamples per second are shown.
--- Date: 28.02.2018 Time: 2:00 PM - 2:30 PM Location: Conference Counter NCC Ost