Conferences and supporting programme
Next Generation 7nm FPGA Architecture Enables Machine Learning for Edge and Cloud Computing
There are three key factors which will drive the definition and adoption of next-generation computing architectures: 1. Need for efficient compute 2. Need for efficient data movement 3. Need for data security In our contribution, we describe the processing architecture of our next generation FPGA, which is highly optimized for ML inference and edge training. Analysis includes characterization of the processing elements for various tasks, ability to flexibly reprogram functionality as well as careful consideration of data flow and memory hierarchy. Moreover, the same architecture is used for both standalone FPGA devices – SpeedsterTM, as well as embedded FPGA IP - SpeedcoreTM. In the latter model, the FPGA IP within the SOC or ASIC acts as a workload specific, reprogrammable hardware acceleration for applications such as AI/Machine learning, Cryptocurrency, 5G infrastructure, Networking and Autonomous driving. This broad portfolio is vital in providing a scalable solution suite, targeting applications from the Data Center to the Edge.
--- Date: 28.02.2019 Time: 9:30 AM - 10:00 AM Location: Conference Counter NCC Ost