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25 - 27 February 2020 // Nuremberg, Germany

Conferences and supporting programme

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CLASS 5.1 How to Secure RISC-V and Cortex-M Embedded Applications

How to Build Hardware-enforced Software-defined Separation in Cortex-M Devices Vortragssprache Englisch

Developing secure embedded devices is becoming more and more difficult. Complex functional requirements are increasingly met with the addition of untrusted 3rd party software. The resulting monolithic firmware presents vastly larger code base, greater attack surface, and increased system vulnerability. When TrustZone is not available, or when its “two worlds” are not suitable for the specific application requirements, developers need an alternative way to shield critical functionality from less trustworthy components. In this class, we’ll show a quick and safe way to add security and separation to ARM Cortex-M devices that don’t have TrustZone. Step by step, we’ll build a hardware-enforced software-defined trusted execution environment capable of enforcing security and separation for a multitude of equally secure “worlds”. We will then configure the trusted execution environment for a real-world 3-zone application controlling a robotic arm, test security and separation, and evaluate overall system performance. NOTE: a number of development boards will be provided for free to the attendees - Microchip SAME70 XPLAINED.

--- Date: 25.02.2020 Time: 16:00 - 18:00 Location: Conference Counter NCC Ost

Speakers

man

Cesare Garlati

/ Hex Five Security / RISC-V Foundation

man

Rangarajan Anand

Microchip Technology Inc.

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