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25 - 27 February 2020 // Nuremberg, Germany

Conferences and supporting programme

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Class 5.2: RISC-V Workshop

How to Build a RISC-V Embedded System In Just 30 Minutes Vortragssprache Englisch

The impressive growth of the RISC-V ecosystem is on everyone’s lips. Originally developed at UC Berkeley, the free and open ISA promises to bring the innovation and collaboration of the open source community to the hardware world - and to dramatically disrupt the whole semiconductor industry in the process. However, hardware and software engineers used to traditional closed-source proprietary architectures and tools may find difficult to orient themselves in this highly-fragmented galaxy of RISC-V technologies, open source tools and development frameworks. So really the question is: How do I get started with RISC-V? In this class, industry veteran Cesare Garlati - long-time member of the non-profit RISC-V Foundation, will show exactly that: how to download, build, configure, debug and test a completely free and open source RISC-V development environment. Specific step-by-step instructions presented in this class - all free / open source: - program the FPGA with a fully customizable RISC-V softcore (Rocket) - build the RISC-V GNU toolchain - both 32bit and 64bits - build the OpenOCD / JTAG debug stack - configure the Eclipse IDE with the RISC-V embedded development plugin - develop, compile, debug and test on actual hardware your first RISC-V “Hello World” application This class is a must-attend for SoC designers, system architects, and software developers who want to get started with RISC-V development but have no time to figure out and assemble all the necessary moving parts.

--- Date: 27.02.2019 Time: 9:30 - 10:30 Location: Conference Counter NCC Ost


 Cesare Garlati

Cesare Garlati

Chief Strategist and Member RISC-V / prpl Foundation


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