Conferences and supporting programme
High Speed Interfaces in Cost Optimized FPGAs
Industrial designs are increasingly requiring higher performance interfaces. Protocols such as DDR4 memory, 10Gigabit Ethernet, JESD204B, Gigabit Ethernet, PCIe and more are becoming commonplace. These higher speed interfaces are often found on high end FPGAs which are often overkill and cost prohibitive. Now there exists a new class of mid-range density FPGAs which are cost optimized, consume lower power and offer smaller form factors. This presentation will explain all of the interfaces discussed above and how they can be utilized in mid-range density FPGAs. Design examples showing these interfaces and steps necessary to implement these functions will be shown. For each design, the typical power consumption will be shown so engineers can judge for themselves the benefits of the new class of mid-range FPGAs. We will go into detail on the FPGA densities offered as well as the package sizes that could be leveraged for embedded designs.
--- Date: 28.02.2018 Time: 11:00 AM - 11:30 AM Location: Conference Counter NCC Ost