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26 - 28 February 2019 // Nuremberg, Germany

Conferences and supporting programme

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Session 5.3: RISC-V III System

Embracing a System Level Approach: Combining Arm & RISC-V in Heterogeneous Designs Vortragssprache Englisch

The open RISC-V CPU architecture is gaining substantial market traction; the ecosystem’s focus is moving from legacy/incumbent processor-centric thinking to system-level issues. Part of that move is a growing realization that many, if not most, designs will include RISC-V in addition to other CPUs and GPUs. Issues of heterogeneous design therefore become key architectural considerations. In addition there needs to be an infrastructure that supports the co-existence of legacy subsystems with new ones such as those implemented using RISC-V. A “system on chip” should be developed as system: not as though it were a collection of independent pieces. This presentation will look at these issues and how they can be addressed. We will provide specific examples, focusing particularly on designs that combine RISC-V and Arm processors within the same SoC.

--- Date: 26.02.2019 Time: 4:30 PM - 5:00 PM Location: Conference Counter NCC Ost

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