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26 - 28 February 2019 // Nuremberg, Germany

Conferences and supporting programme

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Session 10.2 II: SoC II EDA II

Delivering Real Time and Determinism with ... Vortragssprache Englisch

Demand is flourishing in Industrial, Automotive and Avionics applications for implementing real time asymmetric multiprocessing (RTAMP), improving worst case execution time (WCET), reducing latency, isolating and partitioning because software architects want to use application processors cluster like a set of single cores for executing real time code such that software developed for single cores can be reused. Shared resources like the level 2 cache and memory controller guarantee performances on average. Worst case execution time is affected by interference amongst cores when access shared caches and memories. This paper describes how Zynq Ultrascale+ MPSoC and ARM Cortex® A53 clusters can be used with an advanced cache management to improve predictability, determinism and reduction of interference amongst cores. The paper shows how cache management solution is applied to Jailhouse and Xen such that hypervisors behaves more predictable and deterministic. Hypervisor overhead is also reduced making the solution very compelling solution with benchmark and industrial use case.

--- Date: 27.02.2019 Time: 3:00 PM - 3:30 PM Location: Conference Counter NCC Ost

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