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25 - 27 February 2020 // Nuremberg, Germany

Conferences and supporting programme

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Session 5.1: RISC-V I Overview

Compliance Methodology and Initial Results for RISC-V ISA Implementations Vortragssprache Englisch

For most instruction set architectures (ISAs), compliance to the ISA specification is a given. Since all the SoC designers license the RTL from a single source, the RTL complies with the ISA. Similarly the processor IP vendors produce a tool chain to support their ISAs: no compliance issue. Single source provides for consistency, so ecosystems flourish. With the new, open standard RISC-V ISA, the compliance situation is different, because there is no single IP vendor. Compliance testing therefore has become mission-critical for the RISC-V ecosystem. For other ISAs compliance testing has been done by the processor IP vendor, and as a result methodologies and tools for compliance testing have been kept internal, and are not readily available to the industry. This paper introduces the methodology for compliance testing of RISC-V products. The technical issues of determining compliance with the RISC-V ISA are discussed. These issues include providing a framework for development of additional tests, the development of the tests themselves and reference models. Further issues include how to enable users to target the tests at the particular combination of the RISC-V specification subsets that is being used. The questions of completeness and specification coverage are discussed. Use cases are examined, including testing compliance on various proprietary RTL designs, open source RTL designs, FPGAs, SoCs, ISS models and software tools, with issues experienced being explained.

--- Date: 26.02.2019 Time: 12:00 PM - 12:30 PM Location: Conference Counter NCC Ost



Lee Moore

Imperas Software


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