Conferences and supporting programme
Closing the Loop in Additive Manufacturing - An Embedded Solution for Real-Time Melt Pool Monitoring
Laser Metal Deposition (LMD) is a powder-based Additive Manufacturing (AM) process for building up 3D parts layer-by-layer, in which a laser is used to melt metal powder onto a substrate. Due to the requirement of increasing the quality of 3D parts produced through an LMD process, knowledge of correlations between the main process parameters such as laser power, laser head velocity, feed rate and powder mass stream, and the melt pool behavior, is needed. Therefore, the monitoring of the melt pool within a laser deposition process is an essential part of AM, to better understand and control the thermal behavior of the process. In this paper, a novel, vision-based, solution for closing the loop in the AM market is proposed. Our work is based on the real-time monitoring of the LMD process with a comprehensive vision sensing system that interacts with the machine process algorithms in order to detect and correct deposition errors, leading in an optimal shape of the manufactured part or the material properties and contributing towards zero-defect AM. The interoperable vision system is targeted to monitor the size, shape and temperature of the melting pool. The solution performs, on-camera image processing directly on the hardware subsystem’s FPGA for closed-loop AM melting process monitoring. The associated h/w subsystem is comprised of an Optronics CXP6 high-speed camera, equipped with a specific optical system and positioned inside the machine tool head to capture images in-axis with the laser beam. The camera is connected through CoaXPress interface to a frame grabber which utilizes a Xilinx-based FPGA for performing melt pool monitoring pipeline in real-time. The frame grabber focuses on high-speed image acquisition with up to 4*CoaXPress cameras and offers through DMA3600 technology an ultimate access to advanced Machine Vision applications using a visual applets’ based graphical environment. The implementation of the operators in hardware and also in software allows bit-precision simulation of the visual results at every point of the data flow model prior to synthesis. Automatic correction of timing, data synchronization and image border effects are performed by the visual applets simplifying the design process. The synthesis tools of the FPGA manufacturer are integrated into visual applets and produce a hardware applet, following successful completion of a design. In parallel, an SDK project is generated, which can be integrated into an application and can run immediately. The code lists all parameters defined in the design as dynamic operators, which can be changed by the application at runtime. Using the previously described h/w subsystem, results of the melt pool monitoring procedure and parameter estimation will be presented on data coming from different LMD processes, followed by distinctive metrics representing the resourced occupied within the FPGA programming unit such as LUTs, FFs, BRAMs and Emb-ALUs.
--- Date: 28.02.2018 Time: 3:00 PM - 3:30 PM Location: Conference Counter NCC Ost