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26 - 28 February 2019 // Nuremberg, Germany

Conferences and supporting programme

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Session 10 I - Autonomous Systems I / Architectures & Applications

A New Scalable Architecture to Accelerate Deep Convolutional Neural Networks for Low Power IoT Applications Vortragssprache Englisch

Deep Learning is an extremely promising set of techniques that allows achieving state of the art results in many applications involving recognition, identification and/or classification tasks; however, those come at the price of significant requirements in terms of processing power hindering their adoption due to the lack of availability of low-cost and energy-efficient solutions. Recently a push towards an ever-increasing deployment of DL inference on embedded devices supporting the edge-computing paradigm has been observed, overcoming limitations of cloud-based computing for latency, bandwidth requirements, security, privacy, and availability. At the edge, severe performance requirements must coexist with tight constraints in terms of power and energy consumption. Deep Convolutional Neural Networks (CDNN) DL algorithms necessitate billions of multiply-accumulate operations per second for real-time workloads, as well as local storage of millions of bytes of pre-trained weights. To cope with these constraints, low-power IoT end-nodes must resort to specialized hardware blocks for specific compute-intensive data processing, while retaining full software programmability to cope with lower computational-intensity tasks. The STMicroelectronics Orlando is a configurable, scalable and design time parametric CNN Processing Engine powered by an energy efficient set of HW convolutional accelerators supporting kernel compression, an on-chip reconfigurable data transfer fabric to improve data reuse and reduce on-chip and off-chip memory traffic. The Orlando SoC prototype, integrates custom designed DSPs, and a reconfigurable dataflow custom designed HW accelerator fabric connecting camera interfaces, sensor pipelines, croppers, color converters, feature detectors, video encoders, streaming DMAs and 8 convolutional accelerators. The chip includes four SRAM banks each with 1MB, dedicated bus port, and fine-grained power gating, to sustain the maximum throughput for different CDNN topologies reducing the need for external memory to save power. The prototype chip in FD-SOI 28 technology adopts mono-supply SRAM based single well bitcell with low power features and adaptive circuitry to support a wide voltage range from 1.1V to 0.575V, and leverages a GALS clocking architecture to reduce the clock network dynamic power and skew sensitivity due to on-chip variation at lower voltages. A power consumption of 41mW on a typical DCNN algorithm (AlexNet) is achieved with a peak efficiency of 2.9 TOPS/W. The architecture scalability would be described in terms of further optimization and specialization by way of increased HW offloading and memory hierarchy bandwidth reduction and locality exploitation for next generation evolutions from STMicroelectronics. At the end of the presentation, attendees will get good understanding of key challenges associated to low power implementations of DL algorithms and how they can be addressed with solution based on ST technology

--- Date: 27.02.2018 Time: 12:00 PM - 12:30 PM Location: Conference Counter NCC Ost



Dr. Giuseppe Desoli



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