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2 - 4 March 2021 // Nuremberg, Germany

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Exhibitors & Products embedded world 2020
Zoom Image LOGO_RISC-V Verification

RISC-V Verification

LOGO_RISC-V Verification

RISC-V Verification

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Quick and exhaustive verification and proof of compliance to instruction set architecture (ISA) with no gaps or inconsistencies

RISC-V is an open-source hardware instruction set architecture (ISA) widely supported by IP, EDA, and software suppliers. Providers of RISC-V IP cores face a high bar for verification and compliance to the published ISA. Meeting these challenges is essential to successfully compete with older, well established ISAs with many silicon implementations and design-ins. In addition, core providers need to ensure that their designs meet the trust and security expectations of their customers, including the absence of hardware Trojans or other unintended functionality that could enable adversary attacks.

The OneSpin RISC-V Integrity Verification Solution is the industry’s first commercial tool suite to address the needs of both core providers and core integrators. It leverages OneSpin’s advanced formal verification expertise for automotive and other high-integrity processor applications to exhaustively verify the implementation with minimal set up and runtime. The core of the solution is the formalization of the RISC-V ISA as a set of SystemVerilog Assertions (SVA) using the unique OneSpin Operational Assertion approach. Operational SVA enables high-level, non-overlapping assertions that capture end-to-end transactions and requirements in a concise, elegant way:

  • Translate functional requirements in a formal and simulation executable format
  • Capture entire circuit transactions in a concise and elegant way, similar to timing diagrams
  • Achieve 100% functional coverage with high-level and easy-to-review assertions
  • Adopt a consistent assertion style that is applicable to a wide range of applications and able to deliver optimal performances for both simulators and formal tools
  • Cleanly separate implementation-specific supporting verification code from reusable specification-level code
  • Further leverage the assertion set using OneSpin’s GapFreeVerification™ for automatic detection of specification omissions and errors, holes in the verification plan, and unverified RTL functions
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