+++ The entries in the exhibitor & product database correspond to the registration status for embedded world 2020. +++
AndesCore™ is made up of a series of high performance 32-bit CPU core families specially designed to target different market segments of today's emerging embedded applications. The small gate count and high power efficiency AndesCore™ 2- and 3-stage N7 and N8 families are the best candidates to replace 8bit/16bit microcomputer in consumer applications. The N7 and N8 also deliver much better power efficiency (DMIPS/mW) than popular competing 32-bit processors. The AndesCore™ 3-stage S8 family supports the Security Extension Micro Profile of AndeStar architecture. It is a secure processor core capable of code and data protection from physical attacks and malicious debugging. The S8 family is specially suitable for smart card and secure card applications. The AndesCore E8 family targets Internet of Things (IoT) applications with the unique Andes Custom Extension™ (ACE) on a power-efficient compact embedded controller. The E8's unique ACE environment enables designers to specify the architectural element that makes the core ideal for IoT applications. With Andes' Custom-OPtimized Instruction deveLOpment Tools (COPILOT), designers can create custom instructions that differentiate their design from competitive offerings, which are based on standard instruction set processors. By adding special instructions, not easily discoverable by hackers, ACE also provides stronger security to a design.
The 5-stage AndesCore™ N9 family, with its cost-effective features, is ideal for embedded controller market such as general-purpose MCU, automotive control, and storage. The designers can configure certain parameters of the N9 to adjust the CPU's size, power, and performance. The highly performance-efficient AndesCore™ N10 family is ideal for applications ranging from consumer media players and smart glasses all the way to touch panel processing, motor control, and power management. It also comes with I/D cache and local memory options that enable the core to more efficiently perform for networking or communication applications. In addition, with the tightly-coupled IEEE-754 compliant floating point unit (FPU), it can be used in the high precision sensor devices to manipulate the data from ADC which converts physical continuous sensor signals to digital data.
The high-performance AndesCore™ N13 family is designed to address the performance requirements for markets such as home entertainment, digital set top box, networking, and mobile internet device. Complete with a memory management unit and an 8-stage pipeline and supporting a clock rate of over 1GHz, the N13 core delivers an impressive 2.05DMIPS/MHz of performance to serve the most demanding compute environments.
The N(X)25F, D25F, and A(X)25 families are based on Andes' latest AndeStar™ V5 Instruction Set Architecture (ISA), which is compliant to the RISC-V technology. 32-bit N25F/D25F/A25 supports RV32IMAC instruction sets and 64-bit NX25F/AX25 supports RV64IMAC instruction sets. All the 25-series cores supports single (F) and double (D) precision floating point instruction sets. D25F and A(X)25 also supports the P-extension (draft) DSP/SIMD ISA, which is developed by Andes and contributed to the RISC-V foundation. For Linux based applications, MMU (Memory Management Unit) is available on A25/AX25 while PMP (Physical Memory Protection) is available on all V5 cores. Andes extends RISC-V with features including its own instructions to improve performance and functionality, Andes Custom Extension™ (ACE) to create instructions for customized acceleration, half precision floating point load/store instructions to accelerate high precision arithmetic processing, and enhances RISC-V PLIC (Platform-Level Interrupt Controller) with vectored interrupt dispatch and priority-based preemption to speed up interrupt handling. N(X)25F, D25F and A(X)25 are available in platform packages of CPU subsystem pre-integrated with bus controller and peripheral components to facilitate SoC designs.
The versatile and rich features of the AndesCore™ families allow flexible SoC customizations based on the application needs in a design to reduce system power/cost or improve platform performance. AndesCore™ products are available in the form of softcore to broadly satisfy the needs of processor cores in all aspects, including business, market, and technology.
With innovative voltage and frequency scaling protocol and low power memory structure, the AndesCore™ CPU families provide high performance and power-efficiency superior to competing 32-bit cores on the market. In addition, AndesCore™ CPU families employ various commonly-used low power design techniques to save energy and further allows SoC-level power management to regulate operating voltage and frequency for better energy/performance outcome.