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2 - 4 March 2021 // Nuremberg, Germany

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Exhibitors & Products embedded world 2020
Zoom product LOGO_AndeStar™ Architecture

AndeStar™ Architecture

LOGO_AndeStar™ Architecture

AndeStar™ Architecture

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AndeStar™ is a series of patented 32-bit/64-bit RISC-style CPU architecture. Its third generation V3 instruction set includes 16-bit and 32-bit mixed-length instructions to achieve optimal system performance, code density and power efficiency. It has rich configuration features such as 16 or 32 32-bit general purpose registers, DSP instructions, Floating-Point coprocessor instructions, custom coprocessors, and security-enhanced MPU against memory tampering. V3 also has the unique Andes Custom Extension™ (ACE) framework that allows customers to define their own instructions easily and create more differentiations. Its CoDense™ instructions further compact the already very small code size. The GPR (general-purpose registers) based DSP instructions offers an efficient speedup for voice and audio applications as well as image processing. The IEEE-754 compliant Floating-Point coprocessor provides optional single precision or double-and-single precision instructions for fast floating-point computations. Its power management instructions and interface protocol simplify switching among different SoC operating modes related to power and performance. V3 architecture contains optional Memory Protection Unit (MPU) to run secure RTOS and optional Memory Management Unit (MMU) with hardware table walker for virtual memory OS’es such as Linux. It supports a shadow stack pointer register to simplify the protection of the kernel stack pointer. V3 vectored interrupt architecture with priority-based preemption, including 4 priority levels and built-in interrupt controller for up to 32 interrupt sources. All-C Embedded Programming is another major benefit enabled. Software engineers can program startup functions and ISRs (Interrupt Service Routines) in pure C language, and thereby gain higher productivity and reduce maintenance overhead. V3m/V3m+ is the subset of V3 to enable smaller and lower power AndesCore™. V3m/V3m+ instructions are carefully selected from those most commonly used in MCU applications. In addition, V3m/V3m+ also supports the priority-based preemption with built-in vector interrupt controller and All-C Embedded Programming.

Those features and configurability enable AndeStar™ V3 families to support a wide range of applications from low power compact micro-controllers to high-performance Linux-based embedded systems. The unit volume of SoC’s embedded with the V3 family processors has exceeded 2 billions in 2017.

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