Zentel introduces RowHammer-resistant 2Gb and 4Gb DDR3 SDRAM
Zentel Japan Corporation has answered the call of the digital industry for secure SDRAM-ICs. Since the introduction of the DDR3 JEDEC standard years ago a vulnerability of data integrity was enabling even OS-protected parts of DRAM to be corrupted by an exploit of a new DRAM hardware weakness called Row Hammer. Recently by mid 2019 an academic research team published an even more scary discovery, that this DRAM weakness could not just be used by hackers to sabotage data integrity but also for leaking hidden crypto keys or other secret data from OS-protected parts of the DRAM and thus to hijack IoT or cloud networks using a more sophisticated Row-Hammer-based method, which they call RAMBleed https://rambleed.com/ by vastly repeated activation of adjacent word lines more than 200,000 times before refresh.
Above chart shows the number of bit flip failure count under Hot, Room and Low Temperature over numbers of row activation during retention period with zero failures for RowHammer-free enabled versus conventional DDR3 SDRAM. DRAM-integrated Error-Correcting Code (ECC) may help to compensate sporadically occurring single bit flips but cannot prevent any such RowHammer type side channel attacks on critical infrastructure and communication networks.
While threats such as exploits of software flaws can be averted by software updates, this kind of hardware weakness can ultimately only be cured hardware-wise. The new RowHammer-free DDR3 SDRAM-ICs are equipped with an integrated trapping circuit that would detect and block such attacks not affecting the overall performance or current consumption noticeably providing full DDR3 JEDEC compliance and footprint compatibility as drop-in replacement to conventional DDR3 SDRAM. Since switching to conventional DDR4 SDRAM could not solve the problem either, Zentel will next release new Row-Hammer-immune DDR4 versions soon.
Current product overview and DDR3 data sheets: https://zentel-europe.com/productoverview.html