RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
Why RISC-V? Our goals in defining RISC-V include:
A completely open ISA that is freely available to academia and industry.
A real ISA suitable for direct native hardware implementation, not just simulation or binary translation.
An ISA that avoids “over-architecting” for a particular microarchitecture style (e.g., microcoded, in-order, decoupled, out-of-order) or implementation technology (e.g., full-custom, ASIC, FPGA), but which allows efficient implementation in any of these.
An ISA separated into a small base integer ISA, usable by itself as a base for customized accelerators or for educational purposes, and optional standard extensions, to support general-purpose software development.
Support for the revised 2008 IEEE-754 floating-point standard.
An ISA supporting extensive user-level ISA extensions and specialized variants.
32-bit, 64-bit, and 128-bit address space variants for applications, operating system kernels, and hardware implementations.
An ISA with support for highly-parallel multicore or manycore implementations, including heterogeneous multiprocessors.
Optional variable-length instructions to both expand available instruction encoding space and to support an optional dense instruction encoding for improved performance, static code size, and energy efficiency.
A fully virtualizable ISA to ease hypervisor development.
An ISA that simplifies experiments with new supervisor-level and hypervisor-level ISA designs.
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development within the greater RISC-V ecosystem. If your organization is not already a member of the RISC-V Foundation, please visit our membership application page and become part of our engaging RISC-V community.