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25 - 27 February 2020 // Nuremberg, Germany

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Exhibitors & Products embedded world 2020
Zoom product LOGO_Fraunhofer IPMS TSN Ethernet IP Core

Fraunhofer IPMS TSN Ethernet IP Core

LOGO_Fraunhofer IPMS TSN Ethernet IP Core

Fraunhofer IPMS TSN Ethernet IP Core

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Time-Sensitive Networking (TSN) is a set of standards allowing for the timed and prioritized transmission of real-time critical messages over standard Ethernet hardware. With the TSN IP Core, developers at Fraunhofer IPMS provide equipment manufacturers and operators the opportunity to make their devices fit for new TSN standards.

The Fraunhofer IPMS TSN IP Core helps producers and operators of manufacturing and process automation equipment who aim to extend their network devices to meet Time-Sensitive Networking (TSN) standards.. Ethernet TSN is advantageous in that it allows data packets with real-time requirements to be prioritized ahead of less time-critical messages, and time-controlled and deterministically transmitted over standard Ethernet hardware throughout widely ramified networks. Vendor-specific real-time field buses that require specialized hardware support, that are not compliant with IEEE 802.1 and 802.3 standards, and that often interfere with each other are therefore unnecessary.

The Fraunhofer IPMS TSN IP CORE includes hardware modules for time synchronization (IEEE 802.1AS) and data stream management (Traffic Shaping) according to IEEE 802.1 Qav and 802.1Qbv standards as well as a dedicated Ethernet MAC for low latency. Available as a synthesizable source code or a netlist, the IP Core uses standard AMBA® or Avalon® interfaces to facilitate integration with your own circuits and FPGA solutions.

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