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1 - 5 March 2021 // DIGITAL

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MCVS – Intel PSG Cyclone V SMARC2.0 SoM

CycloneV SoC – Maximum Flexibility on a Standard Form Factor

MCVS offers the full flexibility of the Altera Cyclone V SoC FPGA family.  It integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The Altera SoCs combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic.

MCVS features additional hard logic such as PCI Express® Gen1, multiport memory controllers, and high-speed serial transceivers. Our SoCs drive down power and cost while enabling performance levels required by cost-sensitive applications. Due to the flexibility of the MCV concept  25KLE, 40KLE, 85KLE and 110KLE SoC FPGAs are supported by MCVS.

Being compliant to the SMARC2.0 standard defines the key differentiator for MCVS compared to MCV. Main advantages for customers are lower product price as well exchangeability and scalability.


  • Altera Cyclone V SoC FPGA
    • without PCIe support
      • A2: 5CSEBA2U23C8N
        25KLE, 36 DSP blocks
      • A4: 5CSEBA4U23C7N
        40KLE, 58 DSP blocks
      • A5: 5CSEBA5U23C7N
        85KLE, 87 DSP blocks
      • A6: 5CSEBA6U23C7N
        110KLE, 112 DSP blocks
    • with PCIe support
      • C2: 5CSXFC2C6U23C7N
        25KLE, 36 DSP blocks, 6 transceivers 2.5Gbit/s
      • C4: 5CSXFC4C6U23C7N
        40KLE, 58 DSP blocks, 6 transceivers 2.5Gbit/s
      • C5: 5CSXFC5C6U23C7N
        85KLE, 87 DSP blocks, 6 transceivers 2.5Gbit/s
      • C6: 5CSXFC6C6U23C7N
        110KLE, 112 DSP blocks, 6 transceivers 2.5Gbit/s
  • Dual 800 MHz Cortex A9 Cores
  • HPS-Peripherals
  • 1 GByte DDR3 RAM
  • 256 Mbit configuration device
  • 4GByte eMMC memory
  • 143 FPGA signals
  • 66 HPS signals
  • Clock distribution
  • default configuration:
    • Gigabit Ethernet
    • UART
    • CAN
    • SPI
    • I²C
    • USB
  • SMARC2.0 compliant

MCVS- versatile usability at its best

MCVS is of course one of the most flexible System on Module in the embedded market. Thanks to the combination of the Dual Cortex A9 HPS with the FPGA part most application can be addressed with this approach:

MCVS combines FPGA and CPU

MCVS connects the world of FPGA projects with common CPU architecture hardware. A's service is to provide a flawless integration of both areas so that users can focus on the development of application software and/or dedicated FPGA-IP

High Flexibility

Maximum flexibility for using the SoM  with 'exotic' interface requirements. Combining standard IP cores like i.e. display-controller, Ethernet, CAN, serial, I²C, SPI, etc, unique SoM configurations can be used. Benefit from the variety of freely available IP-cores by Altera, or, create your own.

Plug and Play

The SoM supports mainline software for U-Boot and Linux. The BSP covers the entire HPS part of the SoC FPGA. A supplies software development services for drivers, bootloaders and their integration for MCVS.
Your SoC FPGA projects starts in a few minutes.


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