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Use #ew22

15 - 17 March 2022 // Nuremberg, Germany

+++ The entries in the exhibitor & product database correspond to the registration status for embedded world 2020. +++

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Exhibitors & Products embedded world 2020
Zoom Image LOGO_Key-Value-Store (KVS) Accelerator

Key-Value-Store (KVS) Accelerator

LOGO_Key-Value-Store (KVS) Accelerator

Key-Value-Store (KVS) Accelerator

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Xilinx, Fidus Systems and MLE have partnered to address the growing needs in High-Performance Computing and Data Centers to explore “unconventional” data-flow oriented FPGA-based system architecture for acceleration, hyperconvergence, object storage and in-memory compute.
The outcome of this is ZU19SN - a high-capacity, hyperconverged, networked storage node with a Zynq UltraScale+ ZU19EG MPSoC.

Featuring a network accelerator stack plus an out-of-order memory controller, high data throughput can be achieved while balancing between low-latency access and large storage capacities via integrated interfaces to connect to DDR3/DDR4 DRAM, Non-Volatile Memory Express (NVMe) Solid-State Disk (SSD), or SATA/SAS SSD or Harddisks (HDD).

MLE is a licensee of Xilinx and offers sub-licensing, technology support and complementary design services for integrating KVS Accelerator technology into your application.


  • Accelerating Memcached servers in OLTP data center applications.
  • Object storage for hyper-converged storage nodes.
  • Hybrid SSD/HDD Key-Value Drives.

Core Benefits

  • FPGA-based Key-Value load/store processing for data center server CPUs.
  • “Full Accelerator” in programmable logic for line-rate TCP/IP and Memcached processing.
  • Scalable performance to deliver processing speeds at 10, 25, 40, or 100 GigE line rates.
  • Total Server Power reduction via heterogeneous computing architecture.

Key Features

  • Xilinx ZU19EP with dual NVMe m.2 SSDs and QSFP28 for dual 10/25/50/100 GigE.
  • Quad-Core ARM A53 w/ Xilinx PetaLinux.
  • Integrated System-on-Chip solution for Zynq Ultrascale+, or as PCIe-connected companion FPGA.
  • Modular implementation in HDL and C/C++ for Vivado HLS. Supports Xilinx HLx and SDx design flows.
  • Parameterizable for trade-offs between latency and capacity via DRAM, NVMe, SATA, SAS.
  • Fully networked with 10/25/40/100 GigE connectivity.
  • High-performance, low-power - many million responses per second (RPS) at over 200k RPS per Watt
    • 13M RPS at 35 Watts board-level, measured at 10 GigE,
    • 100M RPS, extrapolated for 100 GigE.
  • Tested and benchmarked on object sizes between 128 Bytes to 1M Bytes.
  • Software-defined complete & customizable sub-system based on Xilinx IP cores for out-of-order memory controller, TCP/UDP/IP stack, hash table, DDR3/DDR4 DRAM, NVMe/SATA/SAS SSD and/or HDD interfaces.

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