The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to market the proven TCP/IP & UDP Network Protocol Acceleration Platform (NPAP). This customizable solution enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for multiple links at 1Gbit/s, 10Gbit/s, and beyond.
MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer's ASIC or FPGA project settings, world-wide.
- Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”).
- Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”).
- Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI.
- All MAC / Ethernet / IPv4 / UDP / TCP processing is implemented in HDL code, synthesizable to modern FPGAs.
- User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs.
- Hardware-only implementation of TCP/IP in FPGA
- Networked storage, such as iSCSI
- Test & Measurement connectivity
- Video-over-IP for 3G and 6G transports
- Increase line rates in 10GbE.
- Reduce latency in point-to-point communication.
- Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
- Parameterizable for 8-bit (1GigE) or 128-bit (10GigE, 40GigE) data width
- Multiple, parallel TCP engines for scalable processing
- Network Interface Card functionality with Bypass (optional)
- Point-to-point or LAN capable
- Full line rate of TPRmax = 9.5896 Gbps
- TCP R/W latency of TTR(W) ≥ 1.4 µs
- UDP R/W latency of TUR(W) ≥ 0.75 µs
- Round trip time of RTTmin ≥ 2.25 µs