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2 - 4 March 2021 // Nuremberg, Germany

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Exhibitors & Products embedded world 2020
Zoom Image LOGO_APA7-200: Reconfigurable Xilinx® Artix®-7 FPGA Modules

APA7-200: Reconfigurable Xilinx® Artix®-7 FPGA Modules

LOGO_APA7-200: Reconfigurable Xilinx® Artix®-7 FPGA Modules

APA7-200: Reconfigurable Xilinx® Artix®-7 FPGA Modules

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The AcroPack® product line updates our popular Industry Pack I/O modules with a PCIe interface format. This tech-refresh design offers a compact size, low-cost I/O, the same functionality as the existing Industry Pack modules and a rugged form factor.

The APA7-200 series provides a FPGA based user-configurable bridge between a host processor and a custom digital interface via PCI Express. These boards feature a best in class Artix®-7 interface to deliver the industry’s lowest power and high performance.

Designed for COTS applications these FPGA based digital I/O modules deliver user-customizable I/O, high-density, high-reliability, and high-performance at a low cost.

The APA7-200 series modules are 70mm long. This is 19.05mm longer than the full length mini PCIe card at 50.95mm. The boards width is the same as mPCIe board of 30mm and they use the same mPCIe standard board hold down standoff and screw keep out areas.

A down facing 100 pin Samtec connector mates with the carrier card. Fifty of these pins are available for field I/O signals.

The Engineering Design Kit provides users with basic information required to develop custom FPGA firmware for download to the Xilinx FPGA. Example FPGA design code is provided as a Vivado IP Integrator project for functions such as a one-lane PCI Express interface, DMA, digital I/O control register, and more. Users should be fluent in the use of Xilinx Vivado design tools.

Key Features & Benefits:

■ PCI Express Generation 1 interface

■ Reconfigurable Xilinx® FPGA

■ High channel count digital interface: RS485, LVDS and TTL interface options.

■ 32Mb quad serial Flash memory

■ 33,280 logic cells

■ 41,600 Flip flops

■ 1,800 kb block RAM

■ 90 DSP slices

■ External LVTTL clock input

■ Long distance data transmission

■ Example design

■ Power up and system reset is failsafe

■ Conduction-cooled options


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