Codasip GmbH

Bring your truly unique processing application to life, quickly and easily using Codasip’s unique processor IP generation technology. Do in days what would otherwise take months using traditional methods.

Codasip offers two possible paths to create your unique processor architecture.

RISC-V CORES TAILORING

Hit the ground running by using one of our proven RISC-V cores as the base for your design. Our cores are supplied as modifiable CodAL models (Codasip’s processor modeling language), and can be freely modified to get the exact processor you need. Codasip Studio will guide you through the process to ensure predictable and high quality results.

FROM SCRATCH

Beginning with only the Instruction Accurate (IA) model you can generate a complete SDK for your processor and begin to explore and refine the perfect ISA for your design. Once you are happy with the results, add the additional cycle accurate CA information (pipelining) and generate the complete processor implementation.

Codasip’s RISC-V-based processors (Bk) make use of the rich ecosystem of software and hardware enabled by the extensible, RISC-V Instruction-Set Architecture (ISA) Standard, while retaining the incredible flexibility of all Codasip-made cores.

The SweRV Support Package (SSP) provides a complete set of tools, components and expert advice needed to deploy the SweRV RISC-V core developed by Western Digital. Switching to an open ISA has never been easier!