Andes Technology

10F., No. 1, Sec.3, Gongdao 5th Rd.

East Dist.

30069 Hsinchu City

Taiwan

Phone: +886.3.5726533

www.andestech.com

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Hall 3A / 3A-536

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After 14 years effort starting from scratch, Andes Technology Corporation is now a leading embedded processor intellectual property supplier in the world. We devote ourselves in developing high-performance/low-power 32/64 bit processors and their associated SoC platforms to serve the rapidly growing embedded system applications worldwide.

As the features of electronic devices are becoming more and more versatile, customers demand new generations of SoC solutions for better scalability, flexibility, performance, cost and power saving. However, the diversity of emerging consumer market has driven sophisticated design requirement that incurs vital difficulty for traditional component providers to offer cost-effective solution in time.

The innovative configurable platform solution allows Andes' customers to construct unique system architecture and hardware/software partitioning to gain best optimization in all aspects. With possession of technologies in the areas of processor, system architecture, operating system, software toolchains development, and SoC VLSI implementation, Andes can work closely with customers to shorten their time-to-market with quality design.

Andes' instruction set architecture：AndeStar™ ISA
Andes' embedded processors：AndesCore™ CPUs
Andes' hardware developing platform：AndeShape™ Platform
Andes' software developing platform and toolchains：AndeSight™ IDE
Andes' software supporting system：AndeSoft™ SW Stacks

Looking into electronic system market with heavy competition, when you plan to build an embedded application system with 32/64-bit processor based SoC, you really shall choose Andes with its high-performance/low-power 32/64-bit processors and associated SoC developing platforms to help your team confidently deliver right product to win competition.

It is under the influence of technology that a global village concept is realized; people, and their ideas, are brought closer than ever before. Technology brings forth many positives in life; yet, we could look no further then the ever evident global warming issues to note its negative impact.

With technology rooted deeply in our everyday lives – for, or against it – its advancement is an irreversible process. As a responsible member of the global community, Andes is devoted to develop technology toward the direction of efficiency and economy. We envision our high performance, low power consuming processors and intellectual properties to enter the diverse electronic systems in the present and future, offering resource conserving and affordable technological solutions to every part of the world, truly making “Technology – for better quality of life”.

Andes Custom Extension™

Andes Custom Extension™ (ACE) lets designers design their own CPU instructions on the already performance optimized AndesCore™ processors. With ACE instructions designed specifically for the target applications, they can eliminate the software bottlenecks and significantly improve runtime performances.

Benefits of Custom Instruction Acceleration

Hardwired speedup – use application specific instruction hardware to replace blocks of codes in the original software.
Execution efficiency – reduce the fetch, decode, execute and retire operations of a block of instructions to those of one single ACE instruction. The improvements will be even more significant if an ACE instruction replaces program loops.

Highlights of the ACE features

Scalar Instructions – execute in either a single cycle or multiple cycles.
Vector Instructions – perform a loop operation such as 'for' or 'do while'.
Background instructions – retire immediately from CPU pipeline after issued, but continue the remaining execution in background to achieve parallelism.
Standard operands – ACE instructions can utilize the operands available to the baseline instructions, including immediate constants, general purpose registers and baseline memory (accessed through CPU).
Custom operands – Designers may also use operands based on custom-defined resources such as ACE Register (ACR) and ACE Memory (ACM). ACR and ACM can be in arbitrary width and number as applications require.
Straightforward design flow – SoC designers create ACE definition file to describe the behavior of the ACE instructions, and concise Verilog file to design the hardware logic.
Custom-OPtimized Instruction deveLOpment Tools (COPILOT) – a powerful but simple-to-use ACE design tool that automatically generates required extensions to development tools, ISS simulation and RTL. (Refer to the figure below.)

Benefits of using ACE for Instruction Acceleration

The ACE design environment allows users to focus on instruction functionality, rather than on CPU pipeline and the design process.
The COPILOT tool simplifies engineering work by directly converting the ACE design into a complete environment for the accelerated CPU.
With ACE, adding custom instructions is more like ASIC design since it offloads housekeeping tasks such as opcode selection, instruction decoding, operand mapping/accesses, dependence checking and result gathering. All the housekeeping RTL code is generated by COPILOT.

Standard instructions do not do complex operations or wide I/O. With ACE framework, the SoC designers can do things they have already been doing with Verilog. Also using ACE is small investment to make since designers are already familiar with the C and Verilog standard languages. Powerful but simple ACE language constructs enables users to create more functions with fewer lines of Verilog code, and thus achieves outstanding performance boost and energy reduction.

AndesCore™ Processors

AndesCore™ is made up of a series of high performance 32-bit CPU core families specially designed to target different market segments of today's emerging embedded applications. The small gate count and high power efficiency AndesCore™ 2- and 3-stage N7 and N8 families are the best candidates to replace 8bit/16bit microcomputer in consumer applications. The N7 and N8 also deliver much better power efficiency (DMIPS/mW) than popular competing 32-bit processors. The AndesCore™ 3-stage S8 family supports the Security Extension Micro Profile of AndeStar architecture. It is a secure processor core capable of code and data protection from physical attacks and malicious debugging. The S8 family is specially suitable for smart card and secure card applications. The AndesCore E8 family targets Internet of Things (IoT) applications with the unique Andes Custom Extension™ (ACE) on a power-efficient compact embedded controller. The E8's unique ACE environment enables designers to specify the architectural element that makes the core ideal for IoT applications. With Andes' Custom-OPtimized Instruction deveLOpment Tools (COPILOT), designers can create custom instructions that differentiate their design from competitive offerings, which are based on standard instruction set processors. By adding special instructions, not easily discoverable by hackers, ACE also provides stronger security to a design.

The 5-stage AndesCore™ N9 family, with its cost-effective features, is ideal for embedded controller market such as general-purpose MCU, automotive control, and storage. The designers can configure certain parameters of the N9 to adjust the CPU's size, power, and performance. The highly performance-efficient AndesCore™ N10 family is ideal for applications ranging from consumer media players and smart glasses all the way to touch panel processing, motor control, and power management. It also comes with I/D cache and local memory options that enable the core to more efficiently perform for networking or communication applications. In addition, with the tightly-coupled IEEE-754 compliant floating point unit (FPU), it can be used in the high precision sensor devices to manipulate the data from ADC which converts physical continuous sensor signals to digital data.

The high-performance AndesCore™ N13 family is designed to address the performance requirements for markets such as home entertainment, digital set top box, networking, and mobile internet device. Complete with a memory management unit and an 8-stage pipeline and supporting a clock rate of over 1GHz, the N13 core delivers an impressive 2.05DMIPS/MHz of performance to serve the most demanding compute environments.

The N(X)25F, D25F, and A(X)25 families are based on Andes' latest AndeStar™ V5 Instruction Set Architecture (ISA), which is compliant to the RISC-V technology. 32-bit N25F/D25F/A25 supports RV32IMAC instruction sets and 64-bit NX25F/AX25 supports RV64IMAC instruction sets. All the 25-series cores supports single (F) and double (D) precision floating point instruction sets. D25F and A(X)25 also supports the P-extension (draft) DSP/SIMD ISA, which is developed by Andes and contributed to the RISC-V foundation. For Linux based applications, MMU (Memory Management Unit) is available on A25/AX25 while PMP (Physical Memory Protection) is available on all V5 cores. Andes extends RISC-V with features including its own instructions to improve performance and functionality, Andes Custom Extension™ (ACE) to create instructions for customized acceleration, half precision floating point load/store instructions to accelerate high precision arithmetic processing, and enhances RISC-V PLIC (Platform-Level Interrupt Controller) with vectored interrupt dispatch and priority-based preemption to speed up interrupt handling. N(X)25F, D25F and A(X)25 are available in platform packages of CPU subsystem pre-integrated with bus controller and peripheral components to facilitate SoC designs.

The versatile and rich features of the AndesCore™ families allow flexible SoC customizations based on the application needs in a design to reduce system power/cost or improve platform performance. AndesCore™ products are available in the form of softcore to broadly satisfy the needs of processor cores in all aspects, including business, market, and technology.

With innovative voltage and frequency scaling protocol and low power memory structure, the AndesCore™ CPU families provide high performance and power-efficiency superior to competing 32-bit cores on the market. In addition, AndesCore™ CPU families employ various commonly-used low power design techniques to save energy and further allows SoC-level power management to regulate operating voltage and frequency for better energy/performance outcome.

AndeShape™ Platforms

AndeStar™ Architecture

AndeStar™ is a series of patented 32-bit/64-bit RISC-style CPU architecture. Its third generation V3 instruction set includes 16-bit and 32-bit mixed-length instructions to achieve optimal system performance, code density and power efficiency. It has rich configuration features such as 16 or 32 32-bit general purpose registers, DSP instructions, Floating-Point coprocessor instructions, custom coprocessors, and security-enhanced MPU against memory tampering. V3 also has the unique Andes Custom Extension™ (ACE) framework that allows customers to define their own instructions easily and create more differentiations. Its CoDense™ instructions further compact the already very small code size. The GPR (general-purpose registers) based DSP instructions offers an efficient speedup for voice and audio applications as well as image processing. The IEEE-754 compliant Floating-Point coprocessor provides optional single precision or double-and-single precision instructions for fast floating-point computations. Its power management instructions and interface protocol simplify switching among different SoC operating modes related to power and performance. V3 architecture contains optional Memory Protection Unit (MPU) to run secure RTOS and optional Memory Management Unit (MMU) with hardware table walker for virtual memory OS’es such as Linux. It supports a shadow stack pointer register to simplify the protection of the kernel stack pointer. V3 vectored interrupt architecture with priority-based preemption, including 4 priority levels and built-in interrupt controller for up to 32 interrupt sources. All-C Embedded Programming is another major benefit enabled. Software engineers can program startup functions and ISRs (Interrupt Service Routines) in pure C language, and thereby gain higher productivity and reduce maintenance overhead. V3m/V3m+ is the subset of V3 to enable smaller and lower power AndesCore™. V3m/V3m+ instructions are carefully selected from those most commonly used in MCU applications. In addition, V3m/V3m+ also supports the priority-based preemption with built-in vector interrupt controller and All-C Embedded Programming.

Those features and configurability enable AndeStar™ V3 families to support a wide range of applications from low power compact micro-controllers to high-performance Linux-based embedded systems. The unit volume of SoC’s embedded with the V3 family processors has exceeded 2 billions in 2017.