Cadence Design Systems GmbH

Cadence Sigrity™ PowerSI®, Speed2000™, and OptimizePI™ and SystemSI™ tools

Preventing EMC problems in package and PCB board designs with analysis tools
EMC compliance is required by all commercial electronic devices to ensure safety, compatibility, and reliable operation.  This demo shows you how to include EMC simulations and analysis early in the design stage to help avoid costly redesigns.   The demo will utilize Sigrity™ PowerSI®, Speed2000™, and OptimizePI™ tools to show how SI/PI analysis supports EMC analysis and use postprocessing steps to identify radiated emissions.
 
Identifing IR drop and thermal problems in package and PCB board designs
The demand for thinner, faster, smarter, and higher performance electronics has created new challenges in thermal management.  As the form factor shrinks, power consumption is not reducing proportionally, thus increasing the power density and heat that must be accurately modeled throughout the system.  Electrical-Thermal (E/T) co-simulation plays a much greater role due to the advanced process ICs used in these systems with their lower voltage margins.  This demo shows you how to utilize Sigrity PowerDC integrated electrical-thermal co-simulation to confirm your design has met specified voltage drop and temperature margins.
 
Simulating and verifying your Automotive Ethernet interface is standards compliant
As data rates for communication and serial link interfaces increases, device modeling, interconnect modeling, and analysis methodologies must continue to evolve to address the shrinking design margins and increasingly challenging compliance criteria facing today’s engineers.  In this demo, we will show you how to use the Sigrity PowerSI, OptimizePI and SystemSI™ tools to simulate an Automotive Ethernet system with a channel model and verify the interface is standards compliant.

TensilicaDNA Processor Family

Neural networks are now being developed and deployed in a wide range of markets, from IoT to surveillance to automotive. The computational, power, and memory requirements to process this data are continuously increasing, with new networks and new ways to approach deep learning every day. The Cadence Tensilica DNA processor family offers a much-needed breakthrough in terms of energy efficiency and performance to meet the requirements of on-device artificial intelligence (AI). Our DNA 100 processor is well suited for on-device neural network inference applications spanning autonomous vehicles (AVs), ADAS, surveillance, robotics, drones, augmented reality (AR) /virtual reality (VR), smartphones, smart home and IoT. 
For more information visit the Tensilica DNA Processorwebsite.

The Cadence^® Tensilica^® HiFi 5 DSP for audio and voice, is the first IP core optimized for high-performance far-field processing and artificial intelligence (AI)-based speech recognition processing. This fifth-generation HiFi DSP offers 2X audio processing and 4X neural network (NN) processing improvements versus the HiFi 4 DSP, making it ideal for voice-controlled user interfaces in digital home assistants and automotive infotainment.
Following the popularity of digital home assistants, voice-controlled user interfaces are increasingly important to manufacturers of innovative consumer products. Advanced DSP algorithms are rapidly evolving to eliminate noise and isolate the speakers’ voice for increased understanding, requiring higher processing capabilities and improved energy efficiency. Additionally, NN-based speech recognition algorithms are performing more tasks locally, rather than in the cloud, due to concerns of latency, privacy and network availability.

Key features of the HiFi 5 DSP include:

• Five very long instruction word (VLIW)-slot architecture capable of issuing two 128-bit loads per cycle
• 2X MAC capability versus HiFi 4 DSP for pre- and post-processing, includes:
  • Support for eight 32x32-bit or 16 16x16-bit MACs per cycle
  • Optional eight single-precision floating-point MACs per cycle
• 4X MAC capability versus HiFi 4 DSP for NN processing, includes:
  • 32 16x8 or 16x4 MACs per cycle
  • Optional 16 half-precision floating-point MACs per cycle 
• The new HiFi NN library offers a highly optimized set of library functions commonly used in NN processing (especially speech). These library functions can easily be integrated into popular machine learning frameworks.
• Software compatibility with the complete HiFi product line totaling over 300 HiFi-optimized audio and voice codecs and audio enhancement software packages.

For more information, visit www.cadence.com/go/hifi5

The Cadence^® Tensilica^® Vision Q6 DSP, is the latest DSP for embedded vision and AI built on a new, faster processor architecture. The fifth-generation Vision Q6 DSP offers 1.5X greater vision and AI performance than its predecessor, the Vision P6 DSP, and 1.25X better power efficiency at the Vision P6 DSP’s peak performance. The Vision Q6 DSP is targeted for embedded vision and on-device AI applications in the smartphone, surveillance camera, automotive, augmented reality (AR)/virtual reality (VR), drone and robotics markets. For more information, visit www.cadence.com/go/visionq6.

A deeper, 13-stage processor pipeline and system architecture designed for use with large local memories enable the Vision Q6 DSP to achieve 1.5GHz peak frequency and 1GHz typical frequency at 16nm, in the same floorplan area as the Vision P6 DSP. As a result, designers using the Vision Q6 DSP can develop high-performance products that meet increasing vision and AI demands and power-efficiency needs.

Additional Vision Q6 DSP Features and Benefits

• An enhanced DSP instruction set results in up to 20 percent fewer cycles than the Vision P6 DSP for embedded vision applications/kernels such as Optical Flow, Transpose and warpAffine, and commonly used filters such as Median and Sobel
• 2X system data bandwidth with separate master/slave AXI interfaces for data/instructions and multi-channel DMA alleviates memory bandwidth challenges in vision and AI applications, and also reduces latency and overhead associated with task switching and DMA setup
• Backwards compatibility with the Vision P6 DSP, so customers can preserve their software investment for an easy migration
• Optional vector floating point unit (VFPU) also supports half precision (FP16)

The Vision Q6 DSP supports AI applications developed in the Caffe, TensorFlow and TensorFlowLite frameworks through the Tensilica Xtensa^® Neural Network Compiler (XNNC). The XNNC maps neural networks into executable and highly optimized high-performance code for the Vision Q6 DSP, leveraging a comprehensive set of optimized neural network library functions. The Vision Q6 DSP also supports the Android Neural Network (ANN) API for on-device AI acceleration in Android-powered devices. The software environment also features complete and optimized support for more than 1,500 OpenCV-based vision and OpenVX^™ 1.1 library functions, enabling fast, high-level migration of existing vision applications.

The Vision Q6 DSP builds upon the highly successful Vision P6 DSP, which has been designed into leading mobile application processors including the Kirin 970 from HiSilicon. Both the Vision P6 DSP and the Vision Q6 DSP are designed for general-purpose embedded vision and on-device AI applications requiring performance ranging from 200 to 400 GMAC/sec. With its 384 GMAC/sec peak performance, the Vision Q6 DSP is well suited for high-performance systems and applications. The Vision Q6 DSP can be paired with the Vision C5 DSP for applications requiring greater than 384 GMAC/sec AI performance.

For more information, visit www.cadence.com/go/visionq6.