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26 - 28 February 2019 // Nuremberg, Germany

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Exhibitors & Products embedded world 2019
Zoom product LOGO_Cadence® Functional Safety Solution

Cadence® Functional Safety Solution

LOGO_Cadence® Functional Safety Solution

Cadence® Functional Safety Solution

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Cadence® Functional Safety Solution

The latest ISO 26262 edition 2 standard describes fault injection as the preferred verification methodology for safety critical systems. Cadence demonstrates its safety verification solution for automotive SoCs using fault injection and simulation.

Built on the proven Cadence® Incisive® verification platform, our end-to-end functional safety solution reduces the automotive ISO 26262 compliance effort by 50%. The solution is available as part of the Cadence System Development Suite.

Meeting functional safety requirements calls for:

• Checkers, which monitor the systems and trigger error recovery features when necessary

• Redundancy, which provides continuous function in the event of errors

For their part, safety engineers must implement requirements tracing from the system to components, and ensure that their development flow aligns with tool confidence level (TCL). Functional verification should take place at all levels of abstraction and for all system elements. Safety verification, which measures response of systems to undesired/unplanned events, is another critical step. Finally, to be in full compliance, safety engineers must record and report on all functional safety measures.

Fulfilling the traceability, safety verification, and TCL requirements of ISO 26262, Cadence’s functional safety solution includes Incisive Functional Safety Simulator and a functional safety analysis capability in the Cadence vManager™Metric-Driven Signoff Platform.

Incisive Functional Safety Simulator delivers:

• Seamless reuse of functional and mixed-signal verification environments to accelerate the time to develop safety verification

• Fault identification during elaboration

• Reuse of the existing functional verification environment (with support for SystemVerilog,  Universal Verification Methodology (UVM), and e)

•  Simulation of the unaltered design under test (DUT)

• Support for multiple fault types, including single event upset (SEU), stuck-at-0/stuck-at-1, and single event transient

More information here:

Cadence Tensilica® Vision DSP

LOGO_Cadence Tensilica® Vision DSP

Cadence® Allegro® Sigrity™ solutions

LOGO_Cadence® Allegro® Sigrity™ solutions

Cadence® Protium™ S1 FPGA-Based Prototyping Platform

LOGO_Cadence® Protium™ S1 FPGA-Based Prototyping Platform

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