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25 - 27 February 2020 // Nuremberg, Germany

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Exhibitors & Products embedded world 2019
Zoom product LOGO_DesignWare 56G Ethernet PHY IP

DesignWare 56G Ethernet PHY IP

LOGO_DesignWare 56G Ethernet PHY IP

DesignWare 56G Ethernet PHY IP

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DesignWare 56G Ethernet PHY IP meets the high-performance, low-latency needs of hyperscale data center SoCs requiring 400G and beyond Ethernet data rates. The PHY supports Amplitude Modulation 4-Level (PAM-4) and Non-Return-to-Zero (NRZ) signaling with exceptional signal integrity and jitter performance that exceed specification limits. The high-speed PHY meets the needs of chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects, and its unique and scalable architecture enables next-generation 112G interfaces for 800G Ethernet applications.

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