UltraSoC provides the first, and still only, commercial development and debug environment for RISC-V, including processor trace capabilities. We support all commercial and open source architectures, including those from Andes, Codasip, Microsemi, Roa Logic, SiFive, Syntacore and Western Digital.
Our comprehensive solution includes semiconductor IP and tools support for simple single-core, multi-core, and heterogeneous architectures. In addition to supporting both standards-based and proprietary RISC-V run control and trace requirements, UltraSoC offers a broad range of configurable monitoring and analytics IP, allowing the construction of a sophisticated embedded analytics infrastructure within any SoC. This broad range of IP supports monitoring of all major CPUs and custom logic, and protocol-aware probing of common buses: accelerating verification, bring-up and software debug, and providing valuable insights even when the SoC is deployed in the field.
RISC-V is a new open source instruction set architecture, initially developed by UC Berkeley but now being more widely adopted. As a member of the RISC-V Foundation, UltraSoC is a leading player in defining and implementing the debug architecture for RISC V standards.
Our RISC-V debug solution scales to suit any requirement. If you're developing a cost-sensitive uni-processor chip – for an IoT application, for example – you can use our IP to implement straightforward standards-compliant run-control and JTAG connectivity, supported by our Eclipse-based IDE. At the other end of the complexity spectrum, you can choose a system capable of delivering wire-speed trace and rich information about the operation of even the largest system-level SoC, with multiple CPUs.
UltraSoC fully supports all of the major standards – both established and emerging – for RISC-V debug. And because we can monitor all major CPUs and custom logic, and perform protocol-aware probing of common buses, you can be certain that we can support you, and free you to make the best design choices for your SoC design.