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26 - 28 February 2019 // Nuremberg, Germany

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Exhibitors & Products embedded world 2019

BI-651

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Key Features

  • Architecture: RV64GC
    • 64-bit RISC-V with 32 integer registers (I extension)
    • Integer multiplication and division (M extension)
    • Atomic operation support (A extension)
    • Compressed mode for better code density (C extension)
    • IEEE 754-2008 compliant single and double precision floating point (F+D extensions)
  • Dual instruction issue
  • Up to 4 cores in complex
  • Machine, Supervisor and User modes
  • 8-to-10 stage in-order pipeline
  • Advanced branch predictor: BTB, BHT, RAS
  • Sv39 Virtual Memory support
  • 32 KiB 8-way L1 I-cache
  • 32 KiB 8-way L1 D-cache
  • Integrated 1-2 MiB L2 Cache
  • Interrupts
    • Platform Level Interrupt Controller (PLIC): 127 interrupts with 8 priority levels
    • Multi-Core Local Interruptor (CLINT): timer + software interrupts
  • Integrated debug controller
  • AXI system interface
  • AXI peripheral interface
  • AXI front-port interface for accelerator coherent access
  • Performance
    • 2.18 DMIPS/MHz
    • 3.02 CoreMark/MHz
  • Frequency: 1200 MHz (TSMC, 40nm G, worst setup corner)
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