PGY-SSM SD/SDIO/eMMC Protocol Analyzer is the comprehensive Protocol Analyzer with multiple features to capture and debug communication between host and memory under test. PGY-SSM Protocol Analyzer supports SD, SDIO and eMMC for data rates up to 200MHz DDR mode. PGY-SSM is industry’s first eMMC protocol analyzer that supports version 4.41, 4.51, 5.0 and 5.1 specifications. The innovative active probe has minimum electrical loading on the device under test (DUT) and allows protocol data capture without affecting the performance of the DUT. In an industry-first feature, PGY-SSM protocol analyzer allows continuous streaming of protocol data from PGY-SSM Protocol Analyzer to the host system (using USB3.0 or GbE interface) running the UI. Comprehensive decoding of protocol data, command units, and real time error analysis enable effective verification of communication of SD/SDIO/eMMC host and device.
PGY-SSM Protocol Analyzer enables design and verification engineers to test and debug SD, SDIO and eMMC by triggering on command, response, data or CRC errors. It also provides instantaneous decoding of Command, Response, CID, CSD and Ext CSD registers. The Analytics feature offers easy to analyse graphical representation of command, response, data and frequency of operation for the acquired duration