HDL Coder™ generates portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx® and Altera® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
Native Floating Point, a new technology in HDL Coder, lets you generate synthesizable VHDL or Verilog directly from single-precision Simulink models, eliminating tedious fixed-point conversion, and can even be extended to embedded processors and programmable logic controllers that do not have built-in floating-point units, allowing users to model high dynamic range applications with pure integer hardware