Ashling’s Opella-XD-ARC is a high-speed cJTAG/JTAG debug probe for embedded development on Synopsys’ DesignWare ARC™ configurable RISC cores. Developed in cooperation with Synopsys, the Opella-XD probe integrates with the MetaWare or GNU GDB Debuggers under Windows or Linux based hosts.
Features of Opella-XD-ARC:
• Supports all Synopsys DesignWare ARC processors including HS, EM, ARC 600 and ARC 700
• Up to 100 MHz target cJTAG/JTAG clock rates with autoconditioning support
• Up to 4 MB/s high speed download
• Multi-core debugging support