Don't care from which point of view:
- Timing Specification of DRAM (e. g. Setup/Hold incl. De-Rating)
- Jitter Specification
- Write leveling, Read calibration and all other training mechanism
- Measuring Signal Quality with the Scope and how to connect the probes
- Measuring and evaluating command traces with the logic Analyzer
- Configure the controller via software
- Failure Analysis via Memory Test
- Development of DRAM interfaces from EDO, FPM via SDR to DDR1,2,3,4
- differences between LowPower DRAM (e. g. LPDDR2, LPDDR3) and commodity DRAM
This Seminar answers all your questions about DRAMs
Due to many requests on internal seminars it was not possible to provide a public seminar in 2013. But for fall 2014 we plan a new public seminar. Please Contact us for details.
Beside the DRAM seminar we are offering a Signal Integrity Seminar as well: "Open the Black Box of Signal Integrity"